MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 969

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 14-181
Table 14-182
Freescale Semiconductor
Set up the MII Mgmt for a write cycle to external the PHY AN Advertisement register (write the PHY address and
Set source clock divide by 14, for example, to insure that TSEC_MDC clock speed is not greater than 2.5 MHz.
eTSEC Signals
The AN Advertisement register is at offset address 0x04 from the external PHY address. (in this case 0x11)
GTX_CLK125
MDIO
MDC
describes the shared signals for the RGMII interface.
describes the register initializations required to configure the eTSEC in RGMII mode.
Sum
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
MACSTNADDR2[0110_0000_0000_0010_0000_0000_0000_0000]
MACSTNADDR1[0100_0011_0110_0101_1000_0111_1000_1100]
I/O
I/O
Table 14-182. RGMII Mode Register Initialization Steps
O
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
I
(This example has RGMII 10Mbps mode, Statistics Enable = 1)
MACCFG1[1000_0000_0000_0000_0000_0000_0000_0000]
MACCFG1[0000_0000_0000_0000_0000_0000_0000_0000]
MACCFG2[0000_0000_0000_0000_0111_0010_0000_0101]
MIIMCFG[0000_0000_0000_0000_0000_0000_0000_0101]
MIIMADD[0000_0000_0000_0000_0001_0001_0000_0100]
ECNTRL[0000_0000_0000_0000_0001_0000_0000_0000]
Read MII Mgmt Indicator register and check for Busy = 0,
TBIPA[0000_0000_0000_0000_0000_0000_0001_0000]
Signals
No. of
This indicates that the eTSEC MII Mgmt bus is idle.
1
1
1
3
Table 14-181. Shared RGMII Signals
Assign a Physical address to the TBI,
Setup the MII Mgmt clock speed,
to 02608C:876543, for example.
to 02608C:876543, for example.
Initialize MAC Station Address,
Initialize MAC Station Address,
(I/F Mode = 2, Full Duplex = 1)
GTX_CLK125
GMII Signals
set to 16, for example.
Initialize MACCFG2,
MDIO
MDC
Initialize ECNTRL,
Register address),
Clear Soft_Reset,
Set Soft_Reset,
Sum
I/O
I/O
O
I
Signals
No. of
1
1
1
3
Enhanced Three-Speed Ethernet Controllers
Management interface clock
Management interface I/O
Reference clock
Function
14-221