MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 84

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table
Number
8-22
8-23
8-24
8-25
8-26
8-27
8-28
8-29
8-30
8-31
8-32
8-33
8-34
8-35
8-36
8-37
8-38
8-39
8-40
8-41
8-42
8-43
8-44
8-45
8-46
8-47
8-48
8-49
8-50
8-51
8-52
8-53
8-54
8-55
8-56
8-57
8-58
lxxxiv
DDR_INIT_ADDR Field Descriptions ................................................................................ 8-35
DDR_INIT_EXT_ADDR Field Descriptions....................................................................... 8-35
TIMING_CFG_4 Field Descriptions .................................................................................... 8-36
TIMING_CFG_5 Field Descriptions .................................................................................... 8-38
DDR_ZQ_CNTL Field Descriptions .................................................................................... 8-39
DDR_WRLVL_CNTL Field Descriptions ........................................................................... 8-41
DDR_SR_CNTR Field Descriptions .................................................................................... 8-44
DDR_Register Control Word 1 Field Descriptions .............................................................. 8-45
DDR_Register Control Word 2 Field Descriptions .............................................................. 8-45
DDRDSR_1 Field Descriptions ............................................................................................ 8-46
DDRDSR_2 Field Descriptions ............................................................................................ 8-47
DDRCDR_1 Field Descriptions............................................................................................ 8-49
DDRCDR_2 Field Descriptions............................................................................................ 8-50
DDR_IP_REV1 Field Descriptions ...................................................................................... 8-51
DDR_IP_REV2 Field Descriptions ...................................................................................... 8-51
DATA_ERR_INJECT_HI Field Descriptions....................................................................... 8-52
DATA_ERR_INJECT_LO Field Descriptions ..................................................................... 8-52
ERR_INJECT Field Descriptions ......................................................................................... 8-53
CAPTURE_DATA_HI Field Descriptions............................................................................ 8-53
CAPTURE_DATA_LO Field Descriptions........................................................................... 8-54
CAPTURE_ECC Field Descriptions .................................................................................... 8-54
ERR_DETECT Field Descriptions ....................................................................................... 8-55
ERR_DISABLE Field Descriptions...................................................................................... 8-56
ERR_INT_EN Field Descriptions ........................................................................................ 8-57
CAPTURE_ATTRIBUTES Field Descriptions .................................................................... 8-58
CAPTURE_ADDRESS Field Descriptions .......................................................................... 8-59
CAPTURE_EXT_ADDRESS Field Descriptions ................................................................ 8-59
ERR_SBE Field Descriptions ............................................................................................... 8-60
Byte Lane to Data Relationship ............................................................................................ 8-64
Supported DDR1 SDRAM Device Configurations .............................................................. 8-65
Supported DDR2 SDRAM Device Configurations .............................................................. 8-65
Supported DDR3 SDRAM Device Configurations .............................................................. 8-66
Supported DDR2 SDRAM Device Configurations—One Physical Bank............................ 8-66
DDR2 Address Multiplexing for 64-Bit Data Bus with Interleaving and Partial Array Self
DDR2 Address Multiplexing for 32-Bit Data Bus with Interleaving and Partial Array Self
Example of Address Multiplexing for 64-Bit Data Bus Interleaving between
Example of Address Multiplexing for 64-Bit Data Bus Interleaving
Refresh Disabled .............................................................................................................. 8-67
Refresh Disabled .............................................................................................................. 8-67
Two Banks with Partial Array Self Refresh Disabled...................................................... 8-68
between Four Banks with Partial Array Self Refresh Disabled ....................................... 8-69
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
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