MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 302

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDR Memory Controller
8-28
Bits
25
26
27
28
29
30
31
OBC_CFG
RCW_EN
MD_EN
AP_EN
D_INIT
Name
—
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 8-14. DDR_SDRAM_CFG_2 Field Descriptions (continued)
only be set if DDR3 memories are used. If on-the-fly Burst Chop mode is not used with DDR3
memories, then fixed Burst Chop mode may be used if the proper turnaround times are programmed
into TIMING_CFG_0 and TIMING_CFG_4. DDR_SDRAM_CFG[8_BE] should be cleared for both
on-the-fly Burst Chop mode or fixed Burst Chop mode when using a 64-bit data bus with DDR3
memories.
0 On-the-fly Burst Chop mode is disabled. Fixed burst lengths as defined in
1 On-the-fly Burst Chop mode is used. DDR_SDRAM_CFG[8_BE] should be cleared for on-the-fly
control signals when using registered DIMMs. If address parity is used, the MAPAR_OUT and
MAPAR_ERR pins are used to drive the parity bit and to receive errors from the open-drain parity
error signal. Even parity is used, and parity is generated for the MA[15:0], MBA[2:0], MRAS, MCAS,
MWE signals. Parity does not generate for the MCKE[0:3], MODT[0:3], or MCS[0:3] signals. Note that
address parity should not be used for non-zero values of TIMING_CFG_3[CNTL_ADJ].
0 Address parity is not used
1 Address parity is used
bit before the memory controller is enabled, the controller automatically initializes DRAM after it is
enabled. This bit is automatically cleared by hardware once the initialization is completed. This data
initialization bit should only be set when the controller is idle.
0 There is not data initialization in progress, and no data initialization is scheduled
1 The memory controller initializes memory once it is enabled. This bit remains asserted until the
Reserved
register control words before issuing commands to DRAM. If this bit is set, the controller will write the
register control words after DDR_SDRAM_CFG[MEM_EN] is set, unless DDR_SDRAM_CFG[BI] is
set. The register control words are written with the values in DDR_SDRAM_RCW_1 and
DDR_SDRAM_RCW_2.
0 Register control words will not be automatically written during DRAM initialization
1 Register control words are automatically written during DRAM initialization. This bit should only
Reserved
Mirrored DIMM Enable. Some DDR3 DIMMs are mirrored, where certain MA and MBA pins are
mirrored on one side of the DIMM. When this bit is set, the controller will know to swap these signals
before transmitting to the DRAM. The controller will assume that CS1 and CS3 are the ‘mirrored’
ranks of memory. The following signals are mirrored (MBA[0] vs MBA[1]; MA[3] vs MA[4]; MA[5] vs
MA[6]; MA[7] vs MA[8]).
0 Mirrored DIMMs are not used
1 Mirrored DIMMs are used
On-The-Fly Burst Chop Configuration. Determines if on-the-fly Burst Chop is used. This bit should
Address Parity Enable. Determines if address parity is generated and checked for the address and
DRAM data initialization. This bit is set by software, and it is cleared by hardware. If software sets this
Register Control Word Enable. If DDR3 registered DIMMs are used, it may be necessary to write the
DDR_SDRAM_CFG[8_BE] are used. If fixed Burst Chop is used (with DDR3 memories), then
DDR_SDRAM_CFG[8_BE] should be cleared.
Burst Chop mode. DDR_SDRAM_CFG[DBW] should also be cleared for on-the-fly Burst Chop
mode
initialization is complete. The value in DDR_DATA_INIT register is used to initialize memory.
be set if DDR3 registered DIMMs are used, and the default settings need to be modified.
Description
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