MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 34

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Paragraph
Number
17.1
17.1.1
17.1.1.1
17.1.1.2
17.1.2
17.1.3
17.1.3.1
17.1.3.2
17.2
17.3
17.3.1
17.3.2
17.3.2.1
17.3.2.2
17.3.2.3
17.3.2.4
17.3.2.5
17.3.3
17.3.3.1
17.3.3.2
17.3.3.3
17.3.3.4
17.3.4
17.3.4.1
17.3.4.2
17.3.5
17.3.5.1
17.3.5.1.1
17.3.5.1.2
17.3.5.1.3
17.3.5.1.4
17.3.5.2
17.3.5.2.1
17.3.5.2.2
17.3.5.2.3
xxxiv
Introduction.................................................................................................................... 17-1
External Signal Descriptions ......................................................................................... 17-4
Memory Map/Register Definitions ................................................................................ 17-5
Overview.................................................................................................................... 17-1
Features...................................................................................................................... 17-3
Modes of Operation ................................................................................................... 17-4
PCI Express Memory Mapped Registers................................................................... 17-6
PCI Express Configuration Access Registers.......................................................... 17-10
PCI Express Power Management Event and Message Registers ............................ 17-13
PCI Express IP Block Revision Registers ............................................................... 17-19
PCI Express ATMU Registers ................................................................................. 17-20
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Outbound Transactions .......................................................................................... 17-2
Inbound Transactions............................................................................................. 17-3
Root Complex/Endpoint Modes ............................................................................ 17-4
Link Width ............................................................................................................. 17-4
PCI Express Configuration Address Register (PEX_CONFIG_ADDR) ............ 17-10
PCI Express Configuration Data Register (PEX_CONFIG_DATA)................... 17-10
PCI Express Outbound Completion Timeout Register
PCI Express Configuration Retry Timeout Register
PCI Express Configuration Register (PEX_CONFIG)........................................ 17-12
PCI Express PME and Message Detect Register (PEX_PME_MES_DR) ......... 17-13
PCI Express PME and Message Disable Register
PCI Express PME and Message Interrupt Enable Register
PCI Express Power Management Command Register (PEX_PMCR) ................ 17-18
IP Block Revision Register 1 (PEX_IP_BLK_REV1)........................................ 17-19
IP Block Revision Register 2 (PEX_IP_BLK_REV2)........................................ 17-19
PCI Express Outbound ATMU Registers ............................................................ 17-20
PCI Express Inbound ATMU Registers ............................................................... 17-25
(PEX_OTB_CPL_TOR).................................................................................. 17-11
(PEX_CONF_RTY_TOR)............................................................................... 17-12
(PEX_PME_MES_DISR) ............................................................................... 17-15
(PEX_PME_MES_IER) .................................................................................. 17-16
PCI Express Outbound Translation Address Registers (PEXOTARn) ........... 17-20
PCI Express Outbound Translation Extended Address Registers
PCI Express Outbound Window Base Address Registers
PCI Express Outbound Window Attributes Registers (PEXOWARn)............ 17-22
EP Inbound ATMU Implementation................................................................ 17-25
RC Inbound ATMU Implementation ............................................................... 17-25
PCI Express Inbound Translation Address Registers (PEXITARn)................ 17-26
(PEXOTEARn)............................................................................................ 17-21
(PEXOWBARn) .......................................................................................... 17-22
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