MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 791

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 14-17
Freescale Semiconductor
Bits
0
1
2
THLT0 Transmit halt of ring 0. Set by the eTSEC if is no longer processing transmit frames from this TxBD ring, and
THLT1 Transmit halt of ring 1. Set by the eTSEC if is no longer processing transmit frames from this TxBD ring, and
THLT2 Transmit halt of ring 2. Set by the eTSEC if is no longer processing transmit frames from this TxBD ring, and
Name
describes the fields of the TSTAT register.
DMA from this ring is disabled. To re-start transmission from this TxBD ring, this bit must be cleared by writing
1 to it. This bit is set only on a general error condition (as in IEVENT[TXE]), regardless of TQUEUE[EN0], or
if no ready TxBDs can be fetched. DMACTRL[GTS] being set by the user does not cause this bit to be set.
Software should examine the halted queue's buffer descriptors for repeatable error conditions before taking it
out of the halt state. Failure to do so may cause an effective livelock, in which the error condition recurs and
halts all queues again.
Repeatable error conditions which cause halt include:
Bus error:
TxBD programming errors:
DMA from this ring is disabled. To re-start transmission from this TxBD ring, this bit must be cleared by writing
1 to it. This bit is set only on a general error condition (as in IEVENT[TXE]), regardless of TQUEUE[EN1], or
if no ready TxBDs can be fetched.DMACTRL[GTS] being set by the user does not cause this bit to be set.
Software should examine the halted queue's buffer descriptors for repeatable error conditions before taking it
out of the halt state. Failure to do so may cause an effective livelock, in which the error condition recurs and
halts all queues again.
Repeatable error conditions which cause halt include:
Bus error:
TxBD programming errors:
DMA from this ring is disabled. To re-start transmission from this TxBD ring, this bit must be cleared by writing
1 to it. This bit is set only on a general error condition (as in IEVENT[TXE]), regardless of TQUEUE[EN2], or
if no ready TxBDs can be fetched. DMACTRL[GTS] being set by the user does not cause this bit to be set.
Software should examine the halted queue's buffer descriptors for repeatable error conditions before taking it
out of the halt state. Failure to do so may cause an effective livelock, in which the error condition recurs and
halts all queues again.
Repeatable error conditions which cause halt include:
Bus error:
TxBD programming errors:
• Invalid BD or data address
• Uncorrectable error on BD or data read
• Ready=1 and length=0
• Invalid BD or data address
• Uncorrectable error on BD or data read
• Ready=1 and length=0
• Invalid BD or data address
• Uncorrectable error on BD or data read
• Ready=1 and length=0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 14-17. TSTAT Field Descriptions
Description
Enhanced Three-Speed Ethernet Controllers
14-43