MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 992

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DMA Controller
15-6
0x148
•
•
Offset
0x10C
0x11C
0x13C
0x17C
0x18C
0x19C
0x1A0
0x100
0x104
0x108
0x110
0x114
0x118
0x120
0x124
0x128
0x130
0x134
0x138
0x140
0x144
0x180
0x184
0x188
0x190
0x194
0x198
Mixed indicates a combination of access types.
Special is used when no other category applies. In this case the register figure and field description
table should be read carefully.
–
MR0—DMA 0 mode register
SR0—DMA 0 status register
ECLNDAR0—DMA 0 current link descriptor extended
address register
CLNDAR0—DMA 0 current link descriptor address register
SATR0—DMA 0 source attributes register
SAR0—DMA 0 source address register
DATR0—DMA 0 destination attributes register
DAR0—DMA 0 destination address register
BCR0—DMA 0 byte count register
ENLNDAR0—DMA 0 next link descriptor extended address
register
NLNDAR0—DMA 0 next link descriptor address register
ECLSDAR0—DMA 0 current list descriptor extended
address register
CLSDAR0—DMA 0 current list descriptor address register
ENLSDAR0—DMA 0 next list descriptor extended address
register
NLSDAR0—DMA 0 next list descriptor address register
SSR0—DMA 0 source stride register
DSR0—DMA 0 destination stride register
Reserved
MR1—DMA 1 mode register
SR1—DMA 1 status register
ECLNDAR1—DMA 1 current link descriptor extended
address register
CLNDAR1—DMA 1 current link descriptor address register
SATR1—DMA 1 source attributes register
SAR1—DMA 1 source address register
DATR1—DMA 1 destination attributes register
DAR1—DMA 1 destination address register
BCR1—DMA 1 byte count register
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
DMA Controller Block Base Address: 0x2_1000
Table 15-4. DMA Register Summary
Register
Access
Mixed
Mixed
Mixed
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
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