MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1447

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.6.14.1 Transfer/Transaction Based Interrupts
These interrupt sources are associated with transfer and transaction progress. They are all dependent on
the next interrupt threshold.
21.6.14.1.1 Transaction Error
A transaction error is any error that caused the host controller to think that the transfer did not complete
successfully.
The effects of the error counter and interrupt status are summarized in the following paragraphs. Most of
these errors set the XactErr status bit in the appropriate interface data structure.
There is a small set of protocol errors that relate only when executing a queue head and fit under the
umbrella of a WRONG PID error that are significant to explicitly identify. When these errors occur, the
XactErr status bit in the queue head is set and the Cerr field is decremented. When the PID Code indicates
a SETUP, the following responses are protocol errors and result in XactErr bit being set and the Cerr field
being decremented.
21.6.14.1.2 Serial Bus Babble
When a device transmits more data on the USB than the host controller is expecting for this transaction, it
is defined to be babbling. In general, this is called a Packet Babble. When a device sends more data than
the Maximum Length number of bytes, the host controller sets the Babble Detected bit to a one and halts
Freescale Semiconductor
•
•
•
EPS field indicates a high-speed device and it returns a Nak handshake to a SETUP.
EPS field indicates a high-speed device and it returns a Nyet handshake to a SETUP.
EPS field indicates a low- or full-speed device and the complete-split receives a Nak handshake.
CRC
Timeout
Bad PID
Babble
Buffer Error
1
2
If occurs in a queue head, then USBERRINT is asserted only when Cerr counts down from a one to a
zero. In addition the queue is halted.
The host controller received a response from the device, but it could not recognize the PID as a valid PID.
Event/
Result
Table 21-72
The only method software should use for acknowledging an interrupt is by
transitioning the appropriate status bits in the USBSTS register from a one
to a zero.
2
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Cerr
N/A
N/A
–1
–1
–1
lists the events/responses that the host can observe as a result of a transaction.
Queue Head/qTD/iTD/siTD Side Effects
Table 21-72. Summary of Transaction Errors
See
See
Section 21.6.14.1.2, “Serial Bus Babble”
Section 21.6.14.1.3, “Data Buffer Error”
Status Field
XactErr set
XactErr set
XactErr set
NOTE
USBSTS[USBERRINT]
Universal Serial Bus Interfaces
1
1
1
1
1
1
1
21-113