MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 276

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDR Memory Controller
Figure 8-1
Section 8.5, “Functional Description,”
8.2
The DDR memory controller includes these distinctive features:
8-2
•
•
•
•
•
•
•
Request from
Address from
management
Support for DDR2 and DDR3 SDRAM
64-/72-bit SDRAM data bus. 32-/40-bit SDRAM for DDR2 and DDR3
Programmable settings for meeting all SDRAM timing parameters
The following SDRAM configurations are supported:
— As many as four physical banks (chip selects), each bank independently addressable
— Unbuffered and registered DIMMs
Chip select interleaving support
Partial array self refresh support
Support for data mask signals and read-modify-write for sub-double-word writes. Note that a
read-modify-write sequence is only necessary when ECC is enabled.
Data from
Data from
Features
ECM
SDRAM
To error
is a high-level block diagram of the DDR memory controller with its associated interfaces.
– 64-Mbit to 4-Gbit devices depending on internal device configuration with x8/x16/x32 data
master
master
master
ports (no direct x4 support)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 8-1. DDR Memory Controller Simplified Block Diagram
Signals
Address
Decode
Error
RMW
ECC
contains detailed figures of the controller.
Open
Table
Row
ECC
FIFO
SDRAM
Control
Delay chain
Address
SDRAM
Control
Control
Control
Clock
EN
EN
Freescale Semiconductor
DDR SDRAM
Memory Array
DDR SDRAM
Memory Control
Data Qualifiers
Data Signals
Clocks
MCS[0:3]
MA[15:0]
MCKE[0:3]
MBA[2:0]
MCAS
MRAS
MWE
MDM[0:8]
MODT[0:3]
MDIC[0:1]
MDQS[0:8]
MDQ[0:63]
MECC[0:7]
MCK[0:5]
MCK[0:5]
MDQS[0:8]