MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 988

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DMA Controller
15.1.2
The DMA controller has four high-speed DMA channels. Both the core and external devices can initiate
DMA transfers. All channels are capable of complex data movement and advanced transaction chaining.
Figure 15-1
and block transfers are initiated by each channel. A channel is selected by the arbitration logic and
information is passed to the source and destination control blocks for processing. The source and
destination blocks generate read and write requests to the address tenure engine, which manages the DMA
master port address interface. After a transaction is accepted by the master port, control is transferred to
the data tenure engine that manages the read and write data transfers. A channel remains active in the
shared resources for the duration of the data transfer unless the allotted bandwidth per channel is reached.
15.1.3
The DMA controller offers the following features:
15.1.4
The DMA block has two modes of operation: basic and extended. Basic mode is the DMA legacy mode,
which does not support advanced features. Extended mode supports advanced features such as striding and
flexible descriptor structures.
These two basic modes allow users to initiate and end DMA transfers in various ways.
summarizes the relationship between the modes and the following features:
15-2
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Four high-speed/high-bandwidth channels accessible by local and remote masters
Basic DMA operation modes (direct, simple chaining)
Extended DMA operation modes (advanced chaining and stride capability)
Cascading descriptor chains
Misaligned transfers
Programmable bandwidth control between channels
Three priority levels supported for source and destination transactions
Interrupt on error and completed segment, list, or link
Externally-controlled transfer using DMA_DREQ, DMA_DACK, and DMA_DDONE
Direct mode. No descriptors are involved. Software must initialize the required fields as described
in
Chaining mode. Software must initialize descriptors in memory and the required fields as described
in
Single-write start mode. The DMA process can be started using a single-write command to either
the descriptor address register in one of the chaining modes or the source/destination address
registers in one of the direct modes.
External control capability. This allows an external agent to start, pause, and check the status of a
DMA transfer which has already been initialized.
Table 15-1
Table 15-1
Overview
Features
Modes of Operation
is a high-level block diagram of the DMA controller. Operations such as descriptor fetches
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
before starting a transfer.
before starting a transfer.
Freescale Semiconductor
Table 15-1