MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 316

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDR Memory Controller
8-42
16–19
21–23
Bits
20
WRLVL_SMPL
WRLVL_WLR
Name
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 8-27. DDR_WRLVL_CNTL Field Descriptions (continued)
Write leveling sample time. Determines the number of cycles that must pass before the data
signals are sampled after a DQS pulse during margining mode. This field should be programmed
at least 6 cycles higher than t
prime data bits. This field is only relevant when DDR_WRLVL_CNTL[WRLVL_EN] is set.
0000 Reserved (if DDR_WRLVL_CNTL[WRLVL_EN] is set)
0001 1 clocks
0010 2 clocks
0011 3 clocks
0100 4 clocks
0101 5 clocks
1010 6 clocks
0111 7 clocks
1000 8 clocks
1001 9 clocks
1010 10 clocks
1011 11 clocks
1100 12 clocks
1101 13 clocks
1010 14 clocks
1111 15 clocks
Reserved, should be cleared.
Write leveling repetition time. Determines the number of cycles that must pass between DQS
pulses during write leveling. This field is only relevant when DDR_WRLVL_CNTL[WRLVL_EN] is
set.
000
001
010
011
100
101
110
111
1 clocks
2 clocks
4 clocks
8 clocks
16 clocks
32 clocks
64 clocks
128 clocks
WLO
to allow enough time for propagation delay and sampling of the
Description
Freescale Semiconductor