MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1689

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Index
Debug modes
Descriptor structure, 10-20
DEU
DMA channel 2 and 3 signal select, 23-14
DMA controller
Freescale Semiconductor
self-refresh
signals summary, 8-3
and watchpoint monitor signals summary, 25-5
and watchpoint monitor/trace buffer block diagram, 25-1
DDR signal selection (POR)
DDR source ID debug modes, 25-4, 25-24
DDR/LBC signal selection (POR), 4-23
features, 25-3
functional description, 25-24
LBC source ID debug mode, 13-4, 25-4, 25-24
memory map/register definition, 25-9
modes of operation (set at POR), 25-3
overview, 25-1
PCI/PCI-X
performance monitor events, 24-26
POR status (global utilities), 23-12
READY negation, 4-2
software debug
trace buffer, see Trace buffer
watchpoint, see Watchpoint monitor
FIFOs, 10-117
interrupt control register, 10-66, 10-115
interrupt status register, 10-64, 10-113
IV register, 10-117
key registers, 10-117
key size register, 10-61, 10-110
mode register, 10-58, 10-109
reset control register, 10-62, 10-111
block diagram, 15-1
channel operation, 15-24
organizations supported, 8-64
refresh operation, 8-79
registered DIMM mode, 8-77
timing, 8-72
write timing adjustments, 8-78
operation in sleep mode, 8-82
using forced mode for battery backup, 8-94
see also Signals, DDR
see also Signals, debug
ECC pins used for debug, 4-23
source ID on debug signals, 25-25
source ID on ECC pins, 25-25
source ID debug mode, 25-24
context ID registers, 25-22
bandwidth control, 15-31
power-saving modes, 8-80
timing, 8-80
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
DMA engine, 21-40
DMA_DACK[0:3] (DMA acknowledge) signals, 15-5
DMA_DDONE[0:3] (DMA done) signals, 15-5
DMA_DREQ[0:3] (DMA request) signals, 15-5
Do-Complete-Split state
Do-Start-Split state
DUART
descriptor formats, 15-33
error handling, 15-32
features, 15-2
functional description, 15-24
interrupts, 15-9–15-12, 15-14, 15-19, 15-23, 15-32
limitations and restrictions, 15-36
memory map/register definition, 15-5
modes of operation, 15-2
overview, 15-2
performance monitor events, 24-18
register descriptions, 15-8–15-24
signal select—channel 2 and 3, 23-14
signals summary, 15-4
system considerations, 15-38
transfer interfaces, 15-32
asynchronous, 21-85
periodic interrupt, 21-94
asynchronous, 21-85
periodic interrupt, 21-93
asynchronous communication bits, 12-1
channel abort, 15-31
channel state, 15-31
stride size and distance, 15-32
basic mode transfer, 15-25
channel continue mode for cascading transfer chains,
extended DMA mode transfer, 15-27
external control mode transfer, 15-29
by acronym, see Register Index
see also Signals, DMA controller
unusual scenarios, 15-39
basic chaining mode, 15-26
basic chaining single-write start mode, 15-27
basic direct mode, 15-25
basic direct single-write start mode, 15-26
basic channel continue mode, 15-30
extended mode, 15-31
extended chaining mode, 15-28
extended chaining single-write start mode, 15-28
extended direct mode, 15-27
extended direct single-write start mode, 15-28
DMA to configuration and control registers, 15-39
DMA to DUART, 15-39
DMA to e500 core, 15-39
DMA to I2C, 15-39
15-30
Index-3
D–D