MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 365

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
ACTTOACT
Parameter
WRTORD
ADD_LAT
REFREC
WR_LAT
WRREC
Table 8-69. Programming Differences Between Memory Types (continued)
Refresh Recovery
Write Recovery
Activate A to Activate B
Write to Read Timing
Additive Latency
Write Latency
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Description
DDR3
DDR3
DDR2
DDR3
DDR3
DDR2
DDR3
DDR2
DDR3
DDR2
DDR2
DDR2
Recovery, to the specifications for the memory
used (T
Recovery, to the specifications for the memory
used (T
the memory used (t
the memory used (t
DDR_SDRAM_CFG_2[OBC_CFG] is set, then
this should be programmed to t
cycles.
the memory used (t
the memory used (t
the memory used (t
the memory used (t
If DDR_SDRAM_CFG_2[OBC_CFG] is set, then
this should be programmed to t
cycles.
must be set to a value less than
TIMING_CFG_1[ACTTORW]
must be set to a value less than
TIMING_CFG_1[ACTTORW]
Should be set to CAS latency – 1 cycle. For
example, if the CAS latency if 5 cycles, then this
field should be set to 100 (4 cycles).
Should be set to the desired write latency. Note
that DDR3 SDRAMs do not necessarily require
the write latency to equal the CAS latency minus
1 cycle.
Should be set, along with the Extended Refresh
Should be set, along with the Extended Refresh
Should be set according to the specifications for
Should be set according to the specifications for
Should be set according to the specifications for
Should be set according to the specifications for
Should be set according to the specifications for
Should be set according to the specifications for
Should be set to the desired additive latency. This
Should be set to the desired additive latency. This
RFC
RFC
)
)
Differences
WR
WR
RRD
RRD)
WTR
WTR
)
). If
)
)
)
WR
WTR
+ 2 DRAM
+ 2 DRAM
DDR Memory Controller
Section/page
8.4.1.6/8-19
8.4.1.6/8-19
8.4.1.6/8-19
8.4.1.6/8-19
8.4.1.7/8-21
8.4.1.7/8-21
8-91