MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 775

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.5.3.1.2
The controller ID register (TSEC_ID2) is a read-only register. The TSEC_ID2 register is used to identify
the eTSEC block configuration.
Table 14-6
Table 14-7
14.5.3.1.3
Interrupt events cause bits in the IEVENT register to be set. Software may poll this register at any time to
check for pending interrupts. If an event occurs and its corresponding enable bit is set in the interrupt mask
Freescale Semiconductor
10–15
16–23
24–31
Offset eTSEC1:0x2_4004;
Reset 0
Bits
0–9
W
R
eTSEC3:0x2_6004
0
describes the fields of the TSEC_ID2 register.
describes the field settings for TSEC_ID2[TSEC_INT].
0
TSEC_CFG
TSEC_INT
Controller ID Register (TSEC_ID2)
Interrupt Event Register (IEVENT)
0
Name
—
—
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0
—
0
Bit
10
11
12
13
14
15
Reserved
Interface mode support. See
Reserved
Value identifies configuration options of the eTSEC.
00 eTSEC multiple ring, Rx TOE, Filer and Tx TOE supports are off
F0 eTSEC multiple ring, Rx TOE, Filer and Tx TOE supports are on
30 eTSEC multiple ring support is OFF and Rx TOE, Filer and Tx TOE supports are on
50 eTSEC multiple ring and filer supports are OFF and Rx TOE and Tx TOE supports are on
0
Table 14-7. TSEC_ID2[TSEC_INT] Field Settings
0
0 Ethernet mode not supported
1 Ethernet mode supported
0 FIFO mode not supported
1 FIFO mode supported
Reserved
0 Can be configured to run in FIFO 8-bit mode
1 FIFO 8-bit mode off
0 Can be configured to run in Ethernet normal/full mode
1 Ethernet normal/full mode off
0 Can be configured to run in Ethernet reduced mode
1 Ethernet reduced mode off
Table 14-6. TSEC_ID2 Field Descriptions
0
0
9
Figure 14-3. TSEC_ID2 Register
10
1
1
TSEC_INT
0
0
Table 14-7
0
15 16
0
Mode
0
Description
for settings.
0
0
0
—
0
Enhanced Three-Speed Ethernet Controllers
0
0
23 24
0
1
1
1
TSEC_CFG
Access: Read only
1
0
0
0
14-27
31
0