MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 125

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.3.4.1
The eight-lane SerDes allows use of the three PCI Express controllers. One of the configurations in
Table 1-1
Selection.”
1.3.4.2
The two-lane SerDes allows use of the SATA controllers or of the SGMII interfaces of the eTSEC
controllers (selected at power-on reset). Both lanes must be either SATA or SGMII. See
“SerDes2 I/O Port
1.3.5
Two MPC8536E on-chip enhanced three-speed Ethernet controllers (eTSECs) incorporate a media access
control (MAC) sublayer that supports 10 and 100 Mbps and 1 Gbps Ethernet/802.3 networks with MII,
RMII, GMII, RGMII, TBI, and RTBI physical interfaces as well as SGMII interfaces through a dedicated
SerDes. The eTSECs include 2 Kbyte receive and 10 Kbyte transmit FIFOs and DMA functions.
The MPC8536E eTSECs support programmable CRC generation and checking, RMON statistics, and
jumbo frames of up to 9.6 Kbytes. Frame headers and buffer descriptors (BDs) can be forced into the L2
cache to speed classification or other frame processing. They are designed to comply with IEEE Std.
802.3®, 802.3u®, 802.3x®, 802.3z®, 802.3ac®, 802.3ab®. The BDs are based on the MPC8260 and
MPC860T 10/100 Ethernet programming models. Each eTSEC provides hardware support for
accelerating TCP/IP packet transmission and reception. By default, TCP/IP acceleration is not enabled and
the eTSEC processes frames as pure Ethernet frames, emulating a PowerQUICC III TSEC and allowing
existing driver software to be re-used with minimal change. Key features of these controllers include:
Freescale Semiconductor
•
Flexible configuration for multiple PHY interface configurations. The SGMII interface is available
for any combination of eTSECs, regardless of the configuration of any other eTSEC.
Table 1-2
1
can be selected during power-on reset as described in
8-Bit PCI Express is only available at platform frequency of 527 MHz or greater.
Enhanced Three-Speed Ethernet Controllers (eTSEC)
0/A
Eight-Lane SerDes
Two-Lane SerDes
Ethernet standard interfaces
Ethernet reduced interfaces
FIFO interface
lists available configurations for eTSEC1 and 3.
Selection,” for configuration options.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Mode Option
Table 1-1. Supported SerDes 1 (PCI Express) Configurations
1/B
Table 1-2. Supported eTSEC1 and eTSEC3 Configurations
PEX1 x4
PEX1 x4
2/C
RTBI, RGMII, RMII, or SGMII
PCI Express Signal/Lane
TBI, GMII, or MII
3/D
8-bit FIFO
eTSEC1
PEX1 x8
1
4/E
PEX2 x2
Section 4.4.3.8, “SerDes1 I/O Port
RTBI, RGMII, RMII or SGMII
5/F
PEX2 x4
TBI, GMII, or MII
8-bit FIFO
eTSEC3
6/G
PEX3 x2
Section 4.4.3.9,
7/H
Overview
5