MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1488

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

General Purpose I/O (GPIO)
Table 22-5
22.3.4
The GPIO interrupt event register (GPIER), shown in
caused an interrupt. Each bit in GPIER, corresponds to an interrupt source. GPIER bits are cleared by
writing ones. However, writing zero has no effect.
Table 22-6
22.3.5
The GPIO interrupt mask register (GPIMR), shown in
individual ports. When a masked interrupt request occurs, the corresponding GPIER bit is set, regardless
of the GPIMR state. When one or more non-masked interrupt events occur, the GPIO module issues an
interrupt to the on chip interrupt controller.
Table 22-7
22-4
0–31
0–31
Bits
Bits
Offset 0xC0C
Reset
Offset 0xC10
Reset
W
W
R
R
Name
Name
0
0
D n
D n
defines the bit fields of GPDAT.
defines the bit fields of GPIER.
defines the bit fields of GPIMR.
GPIO Interrupt Event Register (GPIER)
GPIO Interrupt Mask Register (GPIMR)
Data. Write data is latched and presented on external signals if GPDIR has configured the port as an output.
Read operation always returns the data at the signal. Bits D0–D15 correspond to signals GPIO[0:15]. Bits
D16–D31 are unused.
Interrupt events. Indicates whether an interrupt event occurred on the corresponding GPIO signal. Bits
D0–D15 correspond to signals GPIO[0:15]. Bits D16–D31 are unused.
0 No interrupt event occurred on the corresponding GPIO signal.
1 Interrupt event occurred on the corresponding GPIO signal.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 22-5. GPIO Interrupt Event Register (GPIER)
Figure 22-6. GPIO Interrupt Mask Register (GPIMR)
Undefined (the user should write 1s to clear before using)
Table 22-5. GP n DAT Bit Settings
Table 22-6. GPIER Bit Settings
All zeros
Figure
Figure
Description
Description
D n
D n
22-5, carries information of the events that
22-6, defines the interrupt masking for the
Freescale Semiconductor
Access: Read/write
Access: w1c
31
31