MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1120

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Express Interface Controller
17-24
12–15
16–19
20–25
26–31
Bits
Name
OWS
WTT
RTT
—
Read transaction type. Read transaction type to run on the PCI Express link
0000 Reserved
0000 Reserved
0010 Configuration read. Supported only when in RC mode and size of less than or equal to 4 bytes and not
0100 Memory read
...
1000 IO read. Supported only when in RC mode and size of less than or equal to 4 bytes and not crossing
...
1111 Reserved
Write transaction type. Write transaction type to run on the PCI Express link.
0000 Reserved
0001 Reserved
0010 Configuration write. Supported only when in RC mode and size of less than or equal to 4 bytes and not
0100 Memory write
0101 Message write. Only support 4-byte size access on a 4-byte address boundary.
...
1000 IO Write. Supported only when in RC mode and size of less than or equal to 4 bytes and not crossing
...
1111 Reserved
Reserved
Outbound window size. Outbound translation window size N which is the encoded 2
The smallest window size is 4 Kbytes. Note that for the default window (window 0), the outbound window
size may be programmed less than the 64-Gbyte maximum. However, accesses that miss all other windows
and hit outside the default window is aliased to the default window.
000000 Reserved
...
001011 4-Kbyte window size
001100 8-Kbyte window size
...
011111 4-Gbyte window size
100000 8-Gbyte window size
100001 16-Gbyte window size
100010 32-Gbyte window size
100011 64-Gbyte window size
100100 Reserved
...
111111 Reserved
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
crossing 4-byte address boundary.
Reserved
4-byte address boundary.
Reserved
crossing 4-byte address boundary. Note that inbound write transactions on one PCI express port must
not translate to outbound configuration write transactions on another PCI Express port.
Reserved
4-byte address boundary. Note that inbound write transactions on one PCI express port must not
translate to outbound I/O write transactions on another PCI Express port.
Reserved
Table 17-18. PEXOWAR n Field Descriptions (continued)
Description
Freescale Semiconductor
(N + 1)
-byte window size.