MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1019

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.4.4
The DMA engine recognizes list descriptors and link descriptors. List descriptors connect lists of link
descriptors. Link descriptors describe the DMA activity that is to take place. DMA descriptors are built in
either local or remote memory and are connected by the next descriptor fields. Only link descriptors
contain information for the DMA controller to transfer data. Software must ensure that each descriptor is
32-byte aligned. The last link descriptor in the last list in memory sets the NLNDARn[EOLND] bit in the
next link descriptor and NLSDARn[EOLSD] in the next list descriptor fields indicating that these are the
last descriptors in memory. Software initializes the current list descriptor address register to point to the
first list descriptor in memory. The DMA controller traverses through the descriptor lists until the last link
descriptor is met. For each link descriptor in the chain, the DMA controller starts a new DMA transfer with
the control parameters specified by that descriptor. Link and list descriptor fetches always snoop the local
memory space.
Table 15-24
Table 15-25
Freescale Semiconductor
Next list descriptor
extended address
Next list descriptor
address
First link descriptor
extended address
First link descriptor
address
Source stride
Destination stride
Source attributes register
Source address
Destination attributes register Contains destination transaction attributes
Destination address
Next link descriptor extended
address
Descriptor Field
Descriptor Field
DMA Descriptors
summarizes the DMA list descriptors.
summarizes the DMA link descriptors.
Software must ensure that each descriptor is aligned on a 32-byte boundary.
Points to the next list descriptor in memory. After the DMA controller reads the descriptor from memory,
this field is loaded into the next list descriptor extended address registers.
Points to the next list descriptor in memory. After the DMA controller reads the descriptor from memory,
this field is loaded into the next list descriptor address registers.
Points to the first link descriptor in memory for this list. After the DMA controller reads the descriptor from
memory, this field is loaded into the current link descriptor extended address registers.
Points to the first link descriptor in memory for this list. After the DMA controller reads the descriptor from
memory, this field is loaded into the current link descriptor address registers.
Contains the stride information used for the data source if striding is enabled for a link in the list
Contains the stride information used for the data destination if striding is enabled for a link in the list
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Contains source transaction attributes
Contains the source address of the DMA transfer. After the DMA controller reads the descriptor
from memory, this field is loaded into the Source address register.
Contains the destination address of the DMA transfer. After the DMA controller reads the
descriptor from memory, this field is loaded into the destination address register.
Points to the next link descriptor in memory. After the DMA controller reads the link descriptor
from memory, this field is loaded into the extended next link descriptor address registers
Table 15-25. Link DMA Descriptor Summary
Table 15-24. List DMA Descriptor Summary
NOTE
Description
Description
DMA Controller
15-33