MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 401

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.3.3.4
Figure 9-21
Table 9-23
9.3.3.5
Figure 9-22
Table 9-24
Freescale Semiconductor
12–15 MSG n Message interrupts 4–7. Bit 16 represents MSG4; bit 19 represents MSG7.
16–19 MSG n Message interrupts 0–3. Bit 16 represents MSG0; bit 19 represents MSG3.
20–31 EXT n External interrupts . Bit 20 represents IRQ0. Bit 31 represents IRQ11.
0–31
Offset 0x1330
Reset
Bits
8–11
Bits
0–7
Offset 0x1324
Reset
W
R
W
R
Name
Name
0
INT n Internal interrupts 32–63 status. Bit 0 represents INT32. Bit 31 represents INT63.
MSI n Shared message signaled interrupts 0–7. Bit 0 represents MSI0; bit 7 represents MSI7.
0
—
describes the IRQSR2 fields.
describes CISR0 fields.
shows the IRQSR2 fields.
shows CISR0.
MSI0–MSI7
0 The corresponding interrupt is not active or not routed to IRQ_OUT.
1 The corresponding interrupt is active and is routed to IRQ_OUT, if the corresponding x IDR n [EP] is set.
IRQ_OUT Summary Register 2 (IRQSR2)
Critical Interrupt Summary Register 0 (CISR0)
0 The corresponding interrupt is not active or not routed to cint .
1 The corresponding interrupt is active and is routed to cint , if the corresponding x IDR n [CI] is set.
Reserved, should be cleared.
0 The corresponding interrupt is not active or not routed to cint .
1 The corresponding interrupt is active and is routed to cint (if the corresponding x IDR n [CI] is set).
0 The corresponding interrupt is not active or not routed to cint .
1 The corresponding interrupt is active and is routed to cint (if the corresponding x IDR n [CI] is set).
0 The corresponding interrupt is not active or not routed to cint .
1 The corresponding interrupt is active and is routed to cint (if the corresponding x IDR n [CI] is set).
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 9-22. Critical Interrupt Summary Register 0 (CISR0)
Figure 9-21. IRQ_OUT Summary Register 2 (IRQSR2)
7
8
Table 9-23. IRQSR2 Field Descriptions
Table 9-24. CISR0 Field Descriptions
—
11
12
MSG4-MSG7
All zeros
All zeros
IINT n
Description
Description
15
16
MSG0–MSG3
19 20
Programmable Interrupt Controller (PIC)
EXT n
Access: Read only
Access: Read only
9-31
31
31