MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1693

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Index
ID register, 10-54
Initialization
Freescale Semiconductor
initialization/application information, 11-21–11-25
interrupts
memory map/register definition, 11-4
modes of operation, 11-2
overview, 11-2
register descriptions, 11-5
signals summary, 11-3
transaction protocol, 11-11
DDR (initialization and application information), 8-87
ECM (initialization and application information),
eTSEC (initialization and application information),
I
2
C interface (initialization and application information),
control transfer, 11-14
transaction monitoring, 11-14
boot sequencer mode, see I
generation of SCL when SDA low, 11-23
initialization sequence, 11-21
post-transfer software response, 11-22
repeated START generation, 11-23
START generation, 11-12, 11-21
STOP generation, 11-13, 11-22
calling address match condition, 11-6
flowchart for interrupt service routine, 11-24
interrupt after transfer, 11-22
interrupt enable bit (I2CCR[MIEN]), 11-8
interrupt on START, 11-22
interrupt pending status bit (I2CSR[MIF]), 11-10
interrupt-driven byte-to-byte transfers, 11-2
read of last byte, 11-22
slave mode interrupt service routine guidelines, 11-23
boot sequencer mode, 11-2, 11-17–11-20
interrupt-driven byte-to-byte data transfer, 11-2
master mode, 11-2
slave mode, 11-2
by acronym, see Register Index
see also Signals, I
handshaking, 11-16
repeated START condition, 11-3, 11-13
slave address transmission, 11-12
START condition, 11-3, 11-12, 11-21
STOP condition, 11-3, 11-13, 11-22
programming different memory types, 8-89
see also eTSEC, configuration
for slave transmitter routine, 11-23
loss of arbitration, 11-24
7-10–7-11
14-160, 14-207–??
11-21–11-25
mode
2
C
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
2
C interface, boot sequencer
Initialization/application information, 18-14, 20-44
Initiator write, 10-48
Interfaces
Interrupt
Interrupt controller (PIC)
PCI/PCI-X (initialization and application information),
PIC (initialization and application information), 9-58
watchpoint monitor and trace buffer, 25-30
host controller, 21-62
LBC, 13-90–??
USB, 21-2
clear register, 10-54
mask register, 10-50
status register, 10-53
block diagram, 9-1
configuration (global), 9-21
critical interrupts, 9-6, 9-29, 9-31
destination (interrupt routing)
end of interrupt (EOI), 9-51, 9-54
external interrupts
features, 9-2
flow (interrupt processing), 9-52
functional description, 9-52
global timers, 9-23, 9-57
initialization/application information, 9-58
interprocessor interrupts, 9-55
interrupt acknowledge (IACK) signaling, 9-50, 9-54
interrupt routing (mixed mode), 9-6
interrupt source priorities, 9-54
memory map/register definition, 9-9
messaging interrupts, 9-30, 9-31, 9-56
modes of operation, 9-4, 9-21
nesting of interrupts, 9-55
boot sequencer mode, see I
generation of SCL when SDA low, 11-23
initialization sequence, 11-21
post-transfer software response, 11-22
repeated START generation, 11-23
START generation, 11-12, 11-21
STOP generation, 11-13, 11-22
IRQ_OUT, 9-6
routed to critical interrupt (cint), 9-31
routed to IRQ_OUT, 9-30
cascading of timers, 9-27, 9-28
clocking of timers, 9-24, 9-28
RTC (real time clock) signal options, 4-3, 4-26, 9-27,
mixed mode, 9-5
pass-through mode (to support external interrupt
16-67–??
mode
9-28
controllers), 9-5
2
C interface, boot sequencer
Index-7
I–I