MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 291

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.4.1.5
DDR SDRAM timing configuration register 0, shown in
between various SDRAM control commands.
Freescale Semiconductor
20–28
29–31
Offset 0x104
Reset 0 0
Bits
19
W
R
RWT WRT RRT
0
EXT_CASLAT
1
CNTL_ADJ
Name
0 0 0
2
DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
—
3 4
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 8-6. DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
0
5
Extended MCAS latency from READ command. Number of clock cycles between registration of a
READ command by the SDRAM and the availability of the first output data. If a READ command is
registered at clock edge
clock edge
for the total CAS latency. Note that if this bit is set, then 8 clocks are added to the programmed value
in TIMING_CFG_1[CASLAT].
0
Reserved, should be cleared.
Control Adjust. Controls the amount of delay to add to the lightly loaded control signals w/ respect to
all other DRAM address and command signals. The signals affected by this field are MODT[0:3],
MCS[0:3], and MCKE[0:3]
000 MODT[0:3], MCS[0:3], and MCKE[0:3] are launched aligned with the other DRAM address and
001 MODT[0:3], MCS[0:3], and MCKE[0:3] are launched 1/2 platform cycle later than the other
010 MODT[0:3], MCS[0:3], and MCKE[0:3] are launched 1 platform cycle later than the other
011 MODT[0:3], MCS[0:3], and MCKE[0:3] are launched 3/2 platform cycles later than the other
100 MODT[0:3], MCS[0:3], and MCKE[0:3] are launched 2 platform cycles later than the other
101 MODT[0:3], MCS[0:3], and MCKE[0:3] are launched 5/2 platform cycles later than the other
110-111Reserved
WWT — ACT_PD_EXIT
0
6
Table 8-9. TIMING_CFG_3 Field Descriptions (continued)
0
7
0 clocks
control signals.
DRAM address and control signals.
DRAM address and control signals.
DRAM address and control signals.
DRAM address and control signals.
DRAM address and control signals.
8
0
n
0
+
9
m
. This field is concatenated with TIMING_CFG_1[CASLAT] to obtain a 5-bit value
0
11
1
n
and the latency is
12
0
PRE_PD_EXIT
0
0
Figure
Description
15
m
1
clocks, data is available nominally coincident with
16
0 0 0 0
8-6, sets the number of clock cycles
1
—
8 clocks
19 20
ODT_PD_EXIT
0
0
0
23 24
1
DDR Memory Controller
0 0 0 0 0 1 0 1
Access: Read/Write
—
27 28
MRS_CYC
8-17
31