MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 74

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure
Number
17-108
17-109
17-110
17-111
17-112
17-113
17-114
17-115
17-116
17-117
17-118
17-119
17-120
17-121
17-122
17-123
17-124
17-125
17-126
17-127
17-128
17-129
17-130
17-131
17-132
18-1
18-2
18-3
18-4
18-5
18-6
18-7
18-8
18-9
18-10
18-11
18-12
18-13
18-14
18-15
18-16
lxxiv
PCI Express Advanced Error Capabilities and Control Register........................................ 17-87
PCI Express Header Log Register ...................................................................................... 17-88
PCI Express Root Error Command Register....................................................................... 17-89
PCI Express Root Error Status Register.............................................................................. 17-89
PCI Express Correctable Error Source ID Register ............................................................ 17-90
PCI Express Correctable Error Source ID Register ............................................................ 17-90
PCI Express LTSSM State Status Register (PEX_LTSSM_STAT) .................................... 17-91
PCI Express IP Block Core Clock Ratio Register (PEX_GCLK_RATIO) ........................ 17-93
PCI Express Power Management Timer Register (PEX_PM_TIMER) ............................. 17-93
PCI Express PME Time-Out Register (PEX_PME_TIMEOUT) ....................................... 17-94
PCI Express Subsystem Vendor ID Update Register (PEX_SSVID_UPDATE)................ 17-95
PCI Express Configuration Ready Register (PEX_CFG_READY) ................................... 17-95
PCI Express PME_To_Ack Timeout Register (PEX_PME_TO_ACK_TOR) ................... 17-96
PCI Express PCI Interrupt Mask Register (PEX_SS_INTR_MASK)................................ 17-97
Requestor/Completer Relationship ..................................................................................... 17-97
PCI Express High-Level Layering ...................................................................................... 17-98
PCI Express Packet Flow.................................................................................................... 17-98
Address Invariant Byte Ordering—4 bytes Outbound...................................................... 17-100
Address Invariant Byte Ordering—4 bytes Inbound ........................................................ 17-100
Address Invariant Byte Ordering—8 bytes Outbound...................................................... 17-100
Address Invariant Byte Ordering—2 bytes Inbound ........................................................ 17-101
PEX_CONFIG_DATA Byte Ordering.............................................................................. 17-101
PCI Express Error Classification ...................................................................................... 17-107
PCI Express Device Error Signaling Flowchart ............................................................... 17-108
WAKE Generation Example ............................................................................................. 17-116
eSPI Block Diagram.............................................................................................................. 18-1
Single-Master/Multi-Slave Configuration ............................................................................ 18-3
eSPI Mode Register (SPMODE)........................................................................................... 18-6
eSPI Event Register (SPIE)................................................................................................... 18-7
eSPI Mask Register (SPIM).................................................................................................. 18-8
eSPI Command Register (SPCOM)...................................................................................... 18-9
eSPI Transmit Data Register (SPITF)................................................................................. 18-10
SPITF Example—SPMODEx[REVx]=0, SPMODEx[LENx]=3, LSB Sent First ............. 18-10
SPITF Example—SPMODEx[REVx]=x, SPMODEx[LENx]=7 ....................................... 18-10
SPITF Example—SPMODEx[REVx]=0, SPMODEx[LENx]=10, LSB Sent First ........... 18-10
SPITF Example—SPMODEx[REVx]=0, SPMODEx[LENx]=15, LSB Sent First ........... 18-11
SPITF Example—SPMODEx[REVx]=1, SPMODEx[LENx]=15, MSB Sent First .......... 18-11
eSPI Receive Data Register (SPIRF) .................................................................................. 18-11
SPIRF Example—SPMODEx[LENx]=3............................................................................ 18-11
SPIRF Example—SPMODEx[LENx]=10.......................................................................... 18-11
SPIRF Example—SPMODEx[LENx]=15.......................................................................... 18-11
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
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