MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 261

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Part III
Memory, Security, and I/O Interfaces
Part III defines the memory, security and I/O interfaces of the MPC8536E and it describes how these
blocks interact with one another and with other blocks on the device. The following chapters are included:
Freescale Semiconductor
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Chapter 7, “e500 Coherency Module,”
communication between the e500v2 core complex, the L2 cache, and the other blocks that
comprise the coherent memory domain of the MPC8536E.
The ECM permits I/O-initiated transactions to snoop the core complex bus (CCB) of the e500v2
core to maintain coherency across cacheable local memory. It also provides a flexible, easily
expandable switch-type structure for e500v2- and I/O-initiated transactions to be routed
(dispatched) to target modules on the MPC8536E.
Chapter 8, “DDR Memory Controller,”
the MPC8536E. This fully programmable controller supports most DDR memories available
today, including both buffered and unbuffered devices. The built-in error checking and correction
(ECC) ensures very low bit-error rates for reliable high-frequency operation. Dynamic power
management and auto-precharge modes simplify memory system design. Special features like
ECC error injection support rapid system debug.
Chapter 9, “Programmable Interrupt Controller (PIC),”
controller (PIC) of the MPC8536E. The PIC is an OpenPIC-compliant interrupt controller that
provides interrupt management and is responsible for receiving hardware-generated interrupts
from different sources (both internal and external), prioritizing them and delivering them to the
CPU for servicing.
Chapter 10, “Security Engine (SEC) 3.0,”
SEC 3.0 off-loads computationally intensive security functions, such as key generation and
exchange, authentication, and bulk encryption from the processor cores of the MPC8536E. It is
optimized to process all cryptographic algorithms associated with IPsec, IKE, SSL/TLS, iSCSI,
SRTP, 802.11i, 3G, A5/3 for GSM and EDGE, and GEA3 for GPRS.
Chapter 11, “I
This synchronous, serial, bidirectional, multi-master bus allows two-wire connection of devices,
such as microcontrollers, EEPROMs, real-time clock devices, A/D converters and LCDs. The
MPC8536E powers up in boot sequencer mode which allows the I
configuration registers.
Chapter 12, “DUART,”
(UARTs) which feature a PC16552D-compatible programming model. These independent UARTs
are provided specifically to support system debugging.
Chapter 13, “Enhanced Local Bus Controller,”
The main component of the enhanced local bus controller is its memory controller, which provides
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
2
C Interfaces,”
describes the (dual) universal asynchronous receiver/transmitters
describes the inter-IC (IIC or I
defines the e500v2 coherency module and how it facilitates
describes the DDR2/DDR3 SDRAM memory controller of
describes the security controller of the MPC8536E. The
describes the enhanced local bus controller (eLBC).
describes the programmable interrupt
2
C) bus controllers of the MPC8536E.
2
C1 controller to initialize
III-1