MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1124

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Express Interface Controller
17.3.5.2.6
The PCI Express inbound window attributes registers, shown in
translate and other attributes for the translations. 64 Gbytes is the largest window size allowed.
Table 17-22
17-28
Offset Window 1: 0xDF0
Reset 0
12–31
0–11
8–11
Bits
Bits
3–7
0
1
2
W
R
Table 17-21. PCI Express Inbound Window Base Extended Address Register Field Descriptions
Window 2: 0xDD0
Window 3: 0xDB0
EN
0
WBEA Window base extended address. This field corresponds to PCI Express address bits [63:44]
Name
Name
TRGT Target interface. If this field is set to anything other than local memory space, the attributes for the transaction
EN
PF
—
—
—
—
0
1
Table 17-22. PCI Express Inbound Window Attributes Registers Field Descriptions
describes the fields of the PCI Express inbound window attributes registers.
Figure 17-23. PCI Express Inbound Window Attributes Registers (PEXIWAR n )
PCI Express Inbound Window Attributes Registers (PEXIWAR n )
Reserved
PF
Enable. This bit controls the enabling/disabling of the translation window.
0 Disable inbound window translation
1 Enable inbound window translation
Reserved
Prefetchable. This bit indicates that the address space is prefetchable. This bit corresponds to the
prefetchable bit in the BAR in the PCI Express type 0 header. This bit drives the BAR’s prefetchable bit in EP
mode.
0 Not prefetchable
1 Prefetchable
Reserved
must be assigned in a corresponding outbound window at the target. Values not listed below are reserved.
0000 PCI
0001 PCI Express 2—PCI Express controller 2 should not use this encoding
0010 PCI Express 1—PCI Express controller 1 should not use this encoding
0011 PCI Express 3—PCI Express controller 3 should not use this encoding
0100–1110 Reserved
1111 Local memory space
Note: Inbound write transactions on one PCI Express port must not translate to outbound configuration or
2
1
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
3
I/O write transactions on another PCI Express port.
0 0 0
—
0
7
1 1 1
8
TRGT
11 12
1
0 1 0 0
RTT
15 16
Description
Description
0
WTT
1 0 0
Figure
19 20
0 0 0 0 0 0
17-23, define the window sizes to
—
25 26
Freescale Semiconductor
1
Access: Read/Write
0
0
IWS
0
1
31
1