MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1440

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
The start-split transactions do not receive a handshake from the transaction translator, so the host controller
always advances the transfer state in the siTD after the bus transaction is complete. To advance the transfer
state the following operations take place:
These fields are then written back to the memory based siTD. The S-mask is fixed for the life of the current
budget. As mentioned above, TP and T-count are set specifically in each siTD to reflect the data to be sent
from this siTD. Therefore, regardless of the value of S-mask, the actual number of start-split transactions
depends on T-count (or equivalently, Total Bytes to Transfer). The host controller must clear the Active bit
when it detects that all of the schedule data has been sent to the bus. The preferred method is to detect when
T-Count decrements to zero as a result of a start-split bus transaction. Equivalently, the host controller can
detect when Total Bytes to Transfer decrements to zero. Either implementation must ensure that if the
initial condition is Total Bytes to Transfer is equal to zero and T-count is equal to a one, then the host
controller will issue a single start-split, with a zero-length data payload. Software must ensure that TP,
T-count and Total Bytes to Transfer are set to deliver the appropriate number of bus transactions from each
siTD. An inconsistent combination will yield undefined behavior.
If the host experiences hold-offs that cause the host controller to skip start-split transactions for an OUT
transfer, the state of the transfer will not progress appropriately. The transaction translator observes
protocol violations in the arrival of the start-splits for the OUT endpoint (that is, the transaction position
annotation is incorrect as received by the transaction translator).
Example scenarios are described in
Example.”
The host controller can optionally track the progress of an OUT split transaction by setting appropriate bits
in the siTD[C-prog-mask] as it executes each scheduled start-split. The checkPreviousBit() algorithm
defined in
executing each start-split to determine whether start-splits were skipped. The host controller can use this
mechanism to detect missed micro-frames. It can then clear the siTD's Active bit and stop execution of this
siTD. This saves on both memory and high-speed bus bandwidth.
21.6.12.3.5 Periodic Isochronous—Do Complete Split
This state is only used by a split-transaction isochronous IN endpoint. This state is entered unconditionally
from the Do Start State after a start-split transaction is executed for an IN endpoint. Each time the host
controller visits an siTD in this state, it conducts a number of tests to determine whether it should execute
a complete-split transaction. The individual tests are listed below. The sequence they are applied depends
on which micro-frame the host controller is currently executing which means that the tests might not be
applied until after the siTD referenced from the back pointer has been fetched.
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The siTD[Total Bytes To Transfer] and the siTD[Current Offset] fields are adjusted to reflect the
number of bytes transferred.
The siTD[P] (page select) bit is updated appropriately.
The siTD[TP] and siTD[T-count] fields are updated appropriately as defined in
Test A. cMicroFrameBit is bit-wise ANDed with the siTD[C-mask] field. A non-zero result
indicates that software scheduled a complete-split for this endpoint, during this micro-frame. This
test is always applied to a newly fetched siTD that is in this state.
Section 21.6.12.3.5, “Periodic Isochronous—Do Complete Split,”
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Section 21.6.12.3.7, “Split Transaction for Isochronous—Processing
can be used prior to
Freescale Semiconductor
Table
21-69.