MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 398

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Programmable Interrupt Controller (PIC)
Table 9-19
9.3.3
The summary registers indicate the specific interrupt sources routed to the IRQ_OUT or cint0/cint1. PIC
outputs. Summary register bits are cleared when the corresponding interrupt that caused a bit to be set is
negated. Note that only level-sensitive interrupts can be routed to IRQ_OUT or cint0 and cint1.
9-28
16–21
22–23 CLKR Clock ratio. Specifies the ratio of the timer frequency to the CCB clock. The following are supported:
24–28
29–31 CASC Cascade timers. Specifies the output of particular global timers as input to others.
8–14
Bits Name
0–4
5–7
15
ROVR Roll-over control for cascaded timers only. Specifies behavior when count reaches zero by identifying the source
RTM Real time mode. Specifies the clock source for the PIC timers.
—
—
—
—
describes the TCRx fields.
IRQ_OUT and Critical Interrupt Summary Registers
Reserved, should be cleared.
of the reload value. Cascaded timers are always reloaded with their base count value when the more significant
timer in the cascade (the upstream timer) is zero. Bits 5–7 correspond to timers 2–0. Note that global timer 3
always reloads with its GTBCR xn .
0 The timer does not roll over. When the count reaches zero, GTCCR xn is reloaded with the GTBCR xn value.
1 Timer rolls over at zero to all ones. (When the count reaches zero, GTCCR xn is reloaded with 0xFFFF_FFFF.)
000 All timers reload with base count.
001 Timers 1 and 2 reload with base count, timer 0 rolls over (reloads with 0xFFFF_FFFF).
010 Timers 0 and 2 reload with base count, timer 1 rolls over (reloads with 0xFFFF_FFFF).
011 Timer 2 reloads with base count, timers 0 and 1 roll over (reload with 0xFFFF_FFFF).
100 Timers 0 and 1 reload with base count, timer 2 rolls over (reloads with 0xFFFF_FFFF).
101 Timer 1 reloads with base count, timers 0 and 2 roll over (reload with 0xFFFF_FFFF).
110 Timer 0 reloads with base count, timers 1 and 2 roll over (reload with 0xFFFF_FFFF).
111 Timers 0, 1, and 2 roll over (reload with 0xFFFF_FFFF).
Reserved, should be cleared.
0 Timer clock frequency is a ratio of the frequency of the CCB clock as determined by the CLKR field. This is the
1 The RTC signal is used to clock the PIC timers. If this bit is set, the CLKR field has no meaning.
Reserved, should be cleared.
00 Default. Divide by 8
01 Divide by 16
10 Divide by 32
11 Divide by 64
Reserved, should be cleared.
000 Default. Timers not cascaded
001 Cascade timers 0 and 1
010 Cascade timers 1 and 2
011 Cascade timers 0, 1, and 2
100 Cascade timers 2 and 3
101 Cascade timers 0 and 1; timers 2 and 3
110 Cascade timers 1, 2, and 3
111 Cascade timers 0, 1, 2, and 3
default value.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 9-19. TCR x Field Descriptions
Description
Freescale Semiconductor