MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1156

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Express Interface Controller
17.3.8.3.5
The secondary latency timer register does not apply to PCI Express. It must be read-only and return all
zeros when read.
17.3.8.3.6
Note that this device does not support inbound I/O transactions. The I/O base register is shown in
Figure
Offset 0x1C
Table 17-60
17.3.8.3.7
Note that this device does not support inbound I/O transactions. The I/O limit register is shown in
Figure
17-60
Offset 0x1D
Reset
Reset
W
R
W
R
17-62.
17-62.
Bits
7–4
3–0
7
7
describes the I/O base register fields.
PCI Express Secondary Latency Timer Register—0x1B
PCI Express I/O Base Register—0x1C
PCI Express I/O Limit Register—0x1D
Address Decode Type Specifies the number of I/O address bits.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
I/O Start Address
Table 17-61. PCI Express I/O Base Register Field Description
I/O Start Address
I/O Limit Address
Name
Figure 17-63. PCI Express I/O Base Register
Figure 17-64. PCI Express I/O Limit Register
Specifies bits 15:12 of the I/O space start address
0x00 16-bit I/O address decode
0x01 32-bit I/O address decode
All other settings reserved.
4
4
All zeros
All zeros
3
3
Description
Address Decode Type
Address Decode Type
Freescale Semiconductor
Access: Read only
Access: Read only
0
0