MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 128

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Overview
1.3.9
The MPC8536E supports a PCI Express interface compliant with the PCI Express Base Specification
Revision 1.0a. Each controller is configurable at boot time to act as either root complex or endpoint.
The physical layer of the PCI Express interface operates at a 2.5-Gbaud data rate (effective rate of 2 Gbps
due to encoding overhead) per lane. Receive and transmit ports operate independently, resulting in an
aggregate theoretical bandwidth of 32 Gbps (x8 link) or 16 Gbps (x4 link).
Other features of the PCI Express interface include:
1.3.10
The MPC8536E PIC implements the logic and programming structures of the OpenPIC architecture,
providing for external interrupts (with fully nested interrupt delivery), message interrupts, internal-logic
driven interrupts, and global high-resolution timers. Up to 16 programmable interrupt priority levels are
supported.
The PIC can be bypassed to allow use of an external interrupt controller.
1.3.11
The enhanced secure digital host controller (eSDHC) provides an interface between the host system and
SD/MMC cards. The eSDHC acts as a bridge, passing host bus transactions to SD/MMC cards by sending
commands and performing data accesses to or from the cards. Under SD protocol, it can be categorized as
a memory card, I/O card, or combo card. The memory card invokes a copyright protection mechanism that
complies with the security of the SDMI standard.
1.3.12
The enhanced serial peripheral interface (eSPI) allows the device to operate as an SPI master to exchange
data between other PowerQUICC family chips, Ethernet PHYs for configuration, and peripheral devices
such as EEPROMs, real-time clocks, A/D converters, and ISDN devices.
The eSPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire interface
(receive, transmit, clock, and slave select). The eSPI block consists of transmitter and receiver sections, an
independent baud-rate generator, and a control unit. It has the ability to boot from an SPI serial flash
device.
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PMC wake on: LAN activity, USB connection or GPIO, internal timer, or external interrupt event
x8, x4, x2, and x1 link widths supported. x8 PCI Express is only available at CCB (platform) speed
of 527 MHz and above.
Selectable operation as root complex or endpoint
Both 32- and 64-bit addressing and 256-byte maximum payload size
Full 64-bit decode with 36-bit wide windows
PCI Express Controller
Programmable Interrupt Controller (PIC)
Enhanced Secure Digital Host Controller (eSDHC)
eSPI Interface
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Freescale Semiconductor