MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1334

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Secure Digital Host Controller
20.6.6
When polling read or write, once the software begins a buffer read or write, it must access exactly the
number of times as set in the watermark level register, as if a DMA burst occurred.
When the internal DMA is not enabled and a write transaction is in operation, DATPORT (described in
Section 20.4.6, “Buffer Data Port Register
used to read (or write) data by the CPU or external DMA if the data will be written (or read) by the eSDHC
internal DMA.
20-60
Bits
00
01
10
11
Software Restrictions
Command set
Set bits
Clear bits
Write byte
Access Name
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
The command set is changed according to the command set field of the argument
The bits in the pointed byte are set, according to the set bits in the value field.
The bits in the pointed byte are cleared, according to the set bits in the value field.
The value field is written into the pointed byte.
Table 20-28. EXT_CSD Access Modes
(DATPORT)”) must not be read. DATPORT also must not be
Operation
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