MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 624

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DUART
Figure 12-3
Table 12-4
12.3.1.3
The divisor least significant byte register (UDLB) is concatenated with the divisor most significant byte
register (UDMB) to create the divisor used to divide the input clock into the DUART. The output frequency
of the baud generator is 16 times the baud rate; therefore the desired baud rate = platform clock
frequency/(16 [UDMB||UDLB]). Equivalently, [UDMB||UDLB:0b0000] = platform clock
frequency/desired baud rate. Baud rates that can be generated by specific input clock frequencies are
shown in
Figure 12-4
Table 12-5
12-6
Bits
Bits
0–7
0–7
Offset UART0: 0x500, UART1: 0x600
Offset UART0: 0x501, UART1: 0x601
Reset
Reset
UDMB Divisor most significant byte
Name
Name
DATA
Table
W
W
R
R
describes the fields of UTHR.
describes the fields of UDMB registers.
shows the bits in the UTHRs.
shows the bits in the UDMBs.
(ULCR[DLAB] = 1)
Data that is written to UTHR (write only)
Divisor Most and Least Significant Byte Registers (UDMB and UDLB)
12-7.
Figure 12-4. Divisor Most Significant Byte Registers (UDMB0, UDMB1)
0
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 12-3. Transmitter Holding Registers (UTHR n )
Table 12-5. UDMB Field Descriptions
Table 12-4. UTHR Field Descriptions
All zeros
All zeros
UDMB
Description
Description
DATA
Freescale Semiconductor
Access: Read/Write
Access: Write only
7
7