MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 393

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 9-11
9.3.1.8
SVR, shown in
corresponding IACK register is read for a spurious interrupt.
Table 9-12
9.3.2
The two independent groups of global timer registers, group A and group B, are identical in their
functionality, except that they appear at different locations within the PIC register map. Note that each of
the four timers within an x group have four individual configuration registers (GTCCRxn, GTBCRxn,
GTVPRxn, GTDRxn), but they are only shown once in this section. These two groups of timers cannot be
cascaded together.
Freescale Semiconductor
12–15 PRIORITY Priority. Specifies the interrupt priority. The lowest priority is 0 and the highest priority is 15. A priority level of
16–31 VECTOR Vector (Affects only interrupts routed to int ). Contains the value returned when IACK is read and this interrupt
16–31 VECTOR Spurious interrupt vector. Value returned when IACK is read during a spurious vector fetch.
2–11
Bits
0–15
Bits
Offset 0x10E0
Reset 0
0
1
W
R
Name
Name
0
MSK
—
—
A
describes the IPIVPRn fields.
0
describes the SVR fields.
Global Timer Registers
Spurious Vector Register (SVR)
0
Reserved, should be cleared.
“Spurious Vector
Figure
Mask. Mask interrupts to int from this source.
0 An interrupt request is generated if the corresponding IPR bit is set.
1 Further interrupts from this source are disabled.
Activity. Indicates an interrupt has been requested or is in service. The VECTOR and PRIORITY values
should not be changed while this bit is set.
0 No current interrupt activity associated with this source.
1 The interrupt field for this source is set in the IPR or ISR.
Reserved, should be cleared.
0 inhibits signalling of this interrupt to the core. Affects only interrupts routed to int .
resides in the corresponding interrupt request register (IRR) for that core, as shown in
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0
9-10, contains the 16-bit vector returned to the processor core when the
0
0
0
Generation,” gives information about the conditions that may cause a spurious vector fetch.
—
Figure 9-10. Spurious Vector Register (SVR)
0
Table 9-11. IPIVPR n Field Descriptions
Table 9-12. SVR Field Descriptions
0
0
0
0
0
0
15 16
0
Description
Description
1
1
1
1
1
1
Programmable Interrupt Controller (PIC)
1
VECTOR
1
1
1
1
Access: Read/Write
Figure
Section 9.4.1.2.3,
1
1
9-50.
1
1
9-23
31
1