MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 698

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Local Bus Controller
13.4.2.3.4
The timing of the LOE is affected only by TRLX. It always asserts and negates on the rising edge of the
bus clock. LOE asserts either on the rising edge of the bus clock after LCSn is asserted or coinciding with
LCSn (if XACS = 1 and ACS = 10 or ACS = 11). Accordingly, assertion of LOE can be delayed (along
with the assertion of LCSn) by programming TRLX = 1. LOE negates on the rising clock edge coinciding
with LCSn negation
13.4.2.3.5
Slow memory devices that take a long time to disable their data bus drivers on read accesses should choose
some combination of ORn[TRLX,EHTR]. Any access following a read access to the slower memory bank
is delayed by the number of clock cycles specified in
cycle. The final bus turnaround cycle is automatically inserted by the eLBC for reads, regardless of the
setting of ORn[EHTR].
13-56
LBCTL
LCLK
LWE n
LCS n
LALE
LAD
LOE
Output Enable (LOE) Timing
Extended Hold Time on Read Accesses
TA
A
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Address
(XACS = 0, ACS = 00, SCY = 1, CSNT = 1, TRLX = 1)
Figure 13-42. GPCM Relaxed Timing Write
SCY = 1, TRLX = 1
Latched Address
Table 13-7
Write Data
in addition to any existing bus turnaround
CSNT = 1
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