MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 436

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
A channel can signal to the host that it is done with a descriptor by interrupt and/or by a writeback of the
descriptor header into host memory. In the case of interrupt, there is an option to signal after every
descriptor, or only after selected descriptors. In the case of writeback, the value written back is identical to
the header that was read, with the exception that a DONE byte is set to 0xFF. The channels’ done signaling
is described in more detail in
An EU operation can include generating an ICV and then comparing it against a received ICV. The result
of the ICV checking can be signalled to the host either by interrupt or by a writeback of the descriptor
header. If both are enabled, note that the occurrence of an error interrupt prevents the writeback from
occurring. In the case of writeback, the user can opt to do it at end of every descriptor, or only at the end
of descriptors that call for ICV checking.
In case of an error condition in a channel or its reserved EUs, the channel issues an interrupt to the host.
The channel can be configured to either abort the current descriptor and proceed to the next one, or halt
and wait for host intervention.
For more about configuring signaling see
for detail on the writeback fields see
Many security protocols involve both encryption and hashing of packet payloads. To accomplish this
without requiring two passes through the data, channels can configure data flows through two EUs. In such
cases, one EU is designated the “primary EU”, and the other as the “secondary EU”. The primary EU
receives its data from memory through the controller, and the secondary EU receives its data by “snooping”
the SEC buses.
There are two types of snooping:
In the SEC, only MDEU and CRCU are used as secondary EUs.
For more information on the polychannel block, refer to
10.1.3
The controller manages the master and slave interfaces to the system bus and the internal buses that
connect all the various modules. It receives service requests from the host (through the slave interface) and
from the channels, and schedules the required data transfers. The system bus interface and access to system
memory are critical factors in performance, and the 64-bit master and slave interfaces of the SEC controller
enable it to achieve performance unattainable on secondary buses.
The controller enables two modes of operation for the execution units: channel-controlled access and
host-controlled access:
10-6
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Input data can be fed to the primary EU and the same input data snooped by the secondary EU. This
is called “in-snooping”.
Output data from the primary EU can be snooped by the secondary EU. This is called
“out-snooping”.
In channel-controlled access (the SEC’s normal operating mode), all interactions with EUs are
directed by a channel executing a descriptor. The host is involved only in initially supplying the
descriptor pointer and in handling results once descriptor processing is complete.
Controller Overview
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Section 10.4.1.3, “Channel Host
Section 10.3.4, “Link Table Format.”
Section 10.4.4.1, “Channel Configuration Register (CCR)”
Section 10.4, “Polychannel.”
Notification”.
Freescale Semiconductor
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