MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 850

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
14.5.3.6.29 Transmit Pause Control Frame Counter (TXPF)
Figure 14-83
Table 14-87
14.5.3.6.30 Transmit Deferral Packet Counter (TDFR)
Figure 14-84
Table 14-88
14-102
16–31
20–31
0–15
Bits
0–19
Bits
Offset eTSEC1:0x2_46F0;
Reset
Offset eTSEC1:0x2_46F4;
Reset
W
W
R
R
Name
eTSEC3:0x2_66F4
eTSEC3:0x2_66F0
TXPF
Name
TDFR
0
0
—
—
describes the fields of the TXPF register.
describes the fields of the TDFR register.
describes the definition for the TXPF register.
describes the definition for the TDFR register.
Reserved
transmitted with valid CRC and of lengths 64 to 1518 (non VLAN) or 1522 (VLAN).
Transmit PAUSE frame packet counter. Increments each time a valid PAUSE MAC control frame is
Figure 14-83. Transmit Pause Control Frame Counter Register Definition
Reserved
Transmit deferral packet counter. Increments for each frame, which was deferred on its first transmission
attempt. This count does not include frames involved in collisions.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 14-84. Transmit Deferral Packet Counter Register Definition
—
Table 14-88. TDFR Field Descriptions
Table 14-87. TXPF Field Descriptions
—
All zeros
All zeros
15 16
Description
Description
19 20
TXPF
Freescale Semiconductor
TDFR
Access: Read/Write
Access: Read/Write
31
31