MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1195

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.4.1.1
Table 17-119
target.
17.4.1.2
Whenever data must cross a bridge between two busses, the byte ordering of data on the source and
destination buses must be considered. The internal platform bus of this device is inherently big endian and
the PCI Express bus interface is inherently little endian.
There are two methods to handle ordering of data as it crosses a bridge—address invariance and data
invariance. Address invariance preserves the addressing of bytes within a scalar data element, but not the
relative significance of the bytes within that scalar. Conversely, data invariance preserves the relative
significance of bytes within a scalar, but not the addressing of the individual bytes that make up a scalar.
This device uses address invariance as its byte ordering policy.
As stated above, address invariance preserves the byte address of each byte on an I/O interface as it is
placed in memory or moved into a register. This policy can have the effect of reversing the significance
order of bytes (most significant to least significant and vice versa), but it has the benefit of preserving the
Freescale Semiconductor
PCI Express
Transaction
CfgRd0
CfgWr0
CfgRd1
CfgWr1
CplDLk
MRdLk
MsgD
CplLk
IORd
IOWr
CplD
MWr
Msg
Mrd
Cpl
Supported as
Yes (RC only)
Yes (RC only)
Yes (RC only)
Yes (RC only)
Yes (RC only)
Yes (RC only)
Yes (RC only
PCI Express Transactions
Byte Ordering
contains the list of transactions that the PCI Express controller supports as an initiator and a
an Initiator
Yes
Yes
Yes
Yes
Yes
No
No
No
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Supported as
Yes (EP only) Message Request with Data payload. Note that Set_Slot_Power_Limit is the
a Target
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
Table 17-119. PCI Express Transactions
Memory Read Request
Memory Read Lock. As a target, CplLk with UR status is returned.
Memory Write Request to memory-mapped PCI-Express space
I/O Read request. As a target, Cpl with UR status is returned.
I/O Write Request. As a target, Cpl with UR status is returned.
Configuration Read Type 0
Configuration Write Type 0
Configuration Read Type 1. As a target, Cpl with UR status is returned.
Configuration Write Type 1. As a target, Cpl with UR status is returned.
Message Request
only message with data that is supported and then only when the controller is
an initiator and in RC mode or a target and in EP mode.
Completion without Data
Completion with Data
Completion for Locked Memory Read without Data. The only time that CplLk is
returned with UR status is when the controller receives a MRdLk command.
Completion for Locked Memory Read with Data
Definition
PCI Express Interface Controller
17-99