MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1326

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Secure Digital Host Controller
Similar to the write operation, it is possible to meet the ending block of the transfer when paused. In this
case, the eSDHC ignores the stop-at-block-gap request and treats it as a command read operation.
Unlike the write operation, there is no remaining data inside the buffer when the transfer is paused. All
data received before the pause is transferred to the host system. Whether or not a suspend command is sent,
the internal data buffer is not flushed.
If the suspend command is sent and the transfer is later resumed by means of the resume command, the
eSDHC takes the command as a normal one accompanied with data transfer, and it is left for the driver to
set all the relevant registers before the transfer is resumed. If there is only one block to send when the
transfer is resumed, XFERTYP[MSBSEL, BCEN] and IRQSTT[AC12EN] are set. However, the eSDHC
automatically sends CMD12 to mark the end of a multi-block transfer.
20.6.3.3
20.6.3.3.1
At the end of a block transfer, a write CRC status error or read CRC error may occur. For this type of error,
the last block received should be discarded because the integrity of the data block is not guaranteed. It is
recommended to discard the following data blocks and re-transfer the block from the corrupted one. For a
multi-block transfer, the host driver should issue CMD12 to abort the current process and start the transfer
by a new data command. In this scenario, even when the XFERTYP[AC12EN, BCEN] are set, the eSDHC
does not automatically send CMD12 because the last block is not transferred. On the other hand, if it is
within the last block that CRC error occurs, Auto CMD12 is sent by the eSDHC. In this case, the driver
should resend or re-obtain the last block with a single block transfer.
20.6.3.3.2
During the data transfer with the internal DMA, if the DMA engine encounters an error on the platform
bus, the DMA operation is aborted and a DMA error interrupt is sent to the host system. When
acknowledged by such an interrupt, the driver should calculate the start address of the data block where
the error occurred. The start address can be calculated by either of the following methods:
20-52
9. Clear PROCTL[SABGREQ].
10. Check the status bit to see if a read CRC error occurred.
11. Set PROCTL[CREQ] to continue the read operation.
12. Wait for the transfer complete interrupt.
13. Check the status bit to see if a read CRC error or any other errors occurred between sending Auto
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CMD12 and receiving the response.
Read the DSADDR[DSADDR] field. The error occurs during the previous burst. Therefore, by
taking the block size, the previous burst length, and the start address of the next burst transfer into
account, one can obtain the start address of the corrupted block.
Read the BLKATTR[BLKCNT] field. The start address of the corrupted block can be calculated
by the number of blocks left, the total number to transfer, the start address of transfer, and the size
of each block. However, if BCEN is not set, the contents of the block attribute register does not
change and this method does not work.
Transfer Error
CRC Error
Internal DMA Error
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Freescale Semiconductor