MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 699
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MPC8536E-ANDROID
Manufacturer Part Number
MPC8536E-ANDROID
Description
HARDWARE/SOFTWARE ANDROID OS
Manufacturer
Freescale Semiconductor
Series
PowerQUICC ™r
Type
MPUr
Datasheets
1.MPC8536EBVTAVLA.pdf
(127 pages)
2.MPC8536EBVTAVLA.pdf
(2 pages)
3.MPC8536EBVTAVLA.pdf
(1706 pages)
Specifications of MPC8536E-ANDROID
Contents
Board
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 699 of 1706
- Download datasheet (15Mb)
13.4.2.4
External access termination is supported by the GPCM using the asynchronous LGTA input signal, which
is synchronized and sampled internally by the local bus. If, during assertion of LCSn, the sampled LGTA
signal is asserted, it is converted to an internal generation of transfer acknowledge, which terminates the
current GPCM access (regardless of the setting of ORn[SETA]). LGTA should be asserted for at least one
Freescale Semiconductor
LBCTL
LBCTL
LCLK
LCLK
LCS n
LCS n
LALE
LCSy
LALE
LCSy
LAD
LOE
Figure 13-43. GPCM Read Followed by Read (TRLX = 0, EHTR = 0, Fastest Timing)
LAD
LOE
TA
TA
External Access Termination (LGTA)
A
A
Rd. Address
Address 1
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
(TRLX = 0, EHTR = 1, One-Cycle Extended Hold Time on Reads)
Figure 13-44. GPCM Read Followed by Write
Latched Read Address
Latched Address 1
Read Data 1
Read Data
Bus turnaround
Extended hold
Bus turnaround
Address 2
Wr. Address
Latched Address 2
Enhanced Local Bus Controller
Wr. Address
Wr. Data
Data 2
13-57
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