MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 820

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
In full-duplex mode both the carrier sense (CRS) and collision (COL) indications from the PHY are
ignored, but in half-duplex mode the eTSEC defers to CRS, and following a carrier event, times the IPG
using the non-back-to-back IPG configuration values that include support for the optional
two-thirds/one-third CRS deferral process. This optional IPG mechanism enhances system robustness and
ensures fair access to the medium. During the first two-thirds of the IPG, the IPG timer is cleared if CRS
is sensed. During the final one-third of the IPG, CRS is ignored and the transmission begins once IPG is
timed. The two-thirds/one-third ratio is the recommended value.
14.5.3.4.3
While transmitting a packet in half-duplex mode, the eTSEC is sensitive to COL. (Note that in RGMII and
SGMII, there is no COL/CRS. Instead, COL and CRS are derived from the equivalents of RX_DV and
TX_EN.) If a collision occurs, it aborts the packet and outputs the 32-bit jam sequence. The jam sequence
is comprised of several bits of the CRC, inverted to guarantee an invalid CRC upon reception. A signal is
sent to the system indicating that a collision occurred and that the start of the frame is needed for
retransmission. The eTSEC then backs off of the medium for a time determined by the truncated binary
exponential back off (BEB) algorithm. Following this back-off time, the packet is retried. The back-off
time can be skipped if configured through the half-duplex register. However, this is non-standard behavior
and its use must be carefully applied. Should any one packet experience excessive collisions, the packet is
aborted. The system should flush the frame and move to the next one in line. If the system requests to send
a packet while the eTSEC is deferring to a carrier, the eTSEC simply waits until the end of the carrier event
and the timing of IPG before it honors the request.
If packet transmission attempts experience collisions, the eTSEC outputs the jam sequence and waits some
amount of time before retrying the packet. This amount of time is determined by a controlled
randomization process called truncated binary exponential back-off. The amount of time is an integer
number of slot times. The number of slot times to delay before the nth retransmission attempt is chosen as
a uniformly-distributed random integer r in the range:
So after the first collision, the eTSEC backs off either 0 or 1 slot times. After the fifth collision, the eTSEC
backs off between 0 and 32 slot times. After the tenth collision, the maximum number of slot times to back
off is 1024. This can be adjusted through the half-duplex register. An alternate truncation point, such as 7
for instance, can be programmed. On average, the MAC is more aggressive after seven collisions than
other stations on the network.
14.5.3.4.4
Packet flow can be dealt with in a number of ways within eTSEC. A default retransmit attempt limit of 15
can be reduced using the half-duplex register. The slot time or collision window can be used to gate the
retry window and possibly reduce the amount of transmit buffering within the system. The slot time for
10/100 Mbps is 512 bit times. Because the slot time begins at the beginning of the packet (including
preamble), the end occurs around the 56th byte of the frame data. Slot time in 1000-Mbps mode is not
supported.
Full-duplex flow control is provided for in IEEE 802.3x. Currently the standard does not address flow
control in half-duplex environments. Common in the industry, however, is the concept of back pressure.
14-72
0 r
Handling Packet Collisions
Controlling Packet Flow
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MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
k
, where k = min(n,10).
Freescale Semiconductor