MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1237

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

An interrupt coalescing scheme runs on the CCR. When the register contains a value other than
0x0000_0000, an interrupt coalescing timer runs. Each time a command completion is acknowledged, the
timer is reset. When the timer times out, an interrupt is generated.
Table 19-4
19.3.2.4
When a device errors a command by setting the error bit in the status register, this is detected by the SATA
controller as a single device error. The associated command completing due to error is indicated by the
hardware setting the command error bit for that command in the CER (shown in
operation under both command queuing and non-queuing operation, all commands queued into the SATA
controller and at the device are considered aborted. The queue for that device is stopped. The values of the
registers CQR, CAR, and CCR will allow the host software to know which commands have completed
without error and those that were queued at the SATA controller and at the device.
When the host software clears the device error (by writing 1 to DER), the software is also responsible to
clear CER by writing a 1 to the command error bit for the command that was in error. After the error
condition at the device has been cleared, the host application software can reissue the commands to the
SATA controller, which were aborted on the reception of the single device error.
Freescale Semiconductor
Offset 0x1_8010
Offset 0x1_8018
Reset
Reset
•
W
W
R
R
Issuing a command to the command slot
31
31
describes the CCR fields.
Command Error Register (CER)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 19-4. Command Completed Register (CCR)
31–16
15–0
Bit
Figure 19-5. Command Error Register (CER)
—
—
Table 19-4. CCR Field Descriptions
Name
CC n
—
Reserved
Command n completed bit
All zeros
All zeros
16 15
16 15
Description
CC n
CE n
Figure
19-5). For safe
Access: Read only
SATA Controller
Access: w1c
19-7
0
0