MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1168

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Express Interface Controller
17.3.9.7
The PCI Express device capabilities register is shown in
17.3.9.8
The PCI Express device control register is shown in
17-72
Offset 0x54
Reset
Offset 0x50
Reset
Reset
31–28
27–26
25–18
17–15
11–9
Bits
8–6
4–3
2–0
14
13
12
5
W
R
W
W
R
R
—
15
0
—
31
15
0
0
MAX_PL_SIZE_SUP
PCI Express Device Capabilities Register—0x50
PCI Express Device Control Register—0x54
MAX_READ_SIZE
EP_L0s_LAT
PIP
EP_L1_LAT
PHAN_FCT
14
0
14
0
0
CSPLS
CSPLV
Name
Table 17-82. PCI Express Device Capabilities Register Field Description
ABP
PIP
AIP
—
ET
—
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
AIP
1
13
0
0
Figure 17-85. PCI Express Device Capabilities Register
ABP
12
0
28
12
0
0
Figure 17-86. PCI Express Device Control Register
Reserved
Captured Slot Power Limit Scale
Captured Slot Power Limit Value
Reserved
Power Indicator Present
Attention Indicator Present
Attention Button Present
Endpoint L1 Acceptable Latency
Endpoint L0s Acceptable Latency
Extended Tag Field Supported
Phantom Functions Supported
Maximum payload size supported. 001 = 256-bytes
NSE
11
1
27
11
0
0
CSPLS
EP_L1_LAT
APE
10
0
26
0
0
PFE
0
9
25
1
9
0
ETE
0
8
1
0
8
Figure
EP_L0s_LAT
MAX_PAYLOAD_SIZE
Figure
7
0
1
0
17-86.
Description
1
0
6
17-85.
0
CSPLV
ET
1
0
5
0
5
PHAN_FCT
1
0
4
RO
4
1
1
0
3
URR
Freescale Semiconductor
0
3
MAX_PL_SIZE_SUP
18
1
0
2
FER
Access: Read only
Access: Read/write
0
2
17
0
0
NFE
R
0
1
—
CER
16
0
1
0
0
0