MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1058

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Bus Interface
16.3.2.4
The 2-byte PCI bus status register is used to record status information for PCI bus bus-related events. The
definition of each bit is given in
Reads to this register behave normally. Writes are slightly different in that bits can be cleared, but not set.
A bit is cleared whenever the register is written, and the data in the corresponding bit location is a 1. For
example, to clear bit 14 without affecting any other bits in the register, write the value
0b0100_0000_0000_0000 to the register.
16-32
Bits
8
7
6
5
4
3
2
1
0
Memory-write-
Special-cycles Hard-wired to 0, indicating that this PCI controller (as a target) ignores all special-cycle
and-invalidate
Bus master
Parity error
I/O space
response
Memory
PCI Bus Status Register—Offset 0
Name
SERR
space
—
—
Table 16-26. PCI Bus Command Register Field Descriptions (continued)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Controls the PCI_SERR driver of this PCI controller. This bit (and bit 6) must be set to report
address parity errors.
0 Disables the PCI_SERR driver
1 Enables the PCI_SERR driver
Reserved
Controls whether this PCI controller responds to parity errors.
0 Parity errors are ignored and normal operation continues.
1 Parity errors cause the appropriate bit in the PCI status register to be set. However, note that
Reserved
Hard-wired to 0, indicating that this PCI controller, acting as a master, cannot generate the
memory-write-and-invalidate command.
commands.
Indicates whether this PCI controller is configured as a master. This indicates the setting of the
host/agent configuration input signal at power-on reset.
0 Disables the ability to generate PCI accesses
1 Enables this PCI controller to behave as a PCI bus master (Host)
Controls whether this PCI controller (as a target) responds to memory accesses.
0 This PCI controller does not respond to PCI memory space accesses.
1 This PCI controller (as a target) responds to PCI memory space accesses.
Hard-wired to 0, indicating that this PCI controller (as a target) does not respond to PCI I/O
space accesses.
errors are reported based on the values set in the PCI error enable and detection registers.
Table
16-27. Only 2-byte accesses to address offset 0x06 are allowed.
Description
x
06
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