MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 293

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.4.1.6
DDR SDRAM timing configuration register 1, shown in
between various SDRAM control commands.
Freescale Semiconductor
Offset 0x108
Reset
20–23
24–27
28–31
Bits
W
R
0
PRETOACT
ODT_PD_EXIT ODT powerdown exit timing (t
MRS_CYC
Name
DDR SDRAM Timing Configuration 1 (TIMING_CFG_1)
—
3
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 8-7. DDR SDRAM Timing Configuration 1 (TIMING_CFG_1)
4
ACTTOPRE
before ODT may be asserted.
0000 0 clock
0001 1 clock
0010 2 clocks
0011 3 clocks
0100 4 clocks
0101 5 clocks
0110 6 clocks
0111 7 clocks
Reserved, should be cleared.
Mode register set cycle time (t
Register Set command until any other command.
0000 Reserved
0001 1 clock
0010 2 clocks
0011 3 clocks
0100 4 clocks
0101 5 clocks
0110 6 clocks
0111 7 clocks
Table 8-10. TIMING_CFG_0 Field Descriptions (continued)
7
8
ACTTORW
11 12
AXPD
MRD
CASLAT
). Specifies how many clocks must pass after exiting powerdown
). Specifies the number of cycles that must pass after a Mode
All zeros
15 16
Figure
Description
REFREC
1000 8 clocks
1001 9 clocks
1010 10 clocks
1011 11 clocks
1100 12 clocks
1101 13 clocks
1110 14 clocks
1111 15 clocks
1000 8 clocks
1001 9 clocks
1010 10 clocks
1011 11 clocks
1100 12 clocks
1101 13 clocks
1110 14 clocks
1111 15 clocks
8-7, sets the number of clock cycles
19 20
WRREC
23 24 25
— ACTTOACT — WRTORD
DDR Memory Controller
Access: Read/Write
27 28 29
8-19
31