MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 531

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.7.3.6
The CRCU control register stores the coefficients of the residue and static polynomial used in custom CRC
computations.
In
reset value of this register corresponds to the IEEE 802 CRC32 residue and polynomial coefficients. This
register is static in that it is only reset by performing a software reset, and not by an EU reinitialization.
This allows a platform-specific custom polynomial to be written to the register once and used many times.
A context error is generated if this register is written after processing has begun. A polynomial error is
generated if a value is written to this register which does not have a one in bit 0 (representing g
10.7.3.7
The CRCU status register provides general information on the status of the CRCU. A read of the status
register captures a snapshot of CRCU’s operating state at a particular moment in time. Of notable interest
to the user are the three interrupt flags (error interrupt, done interrupt, and reset done). Writes to this
register are ignored.
Freescale Semiconductor
Offset 0x3_F028
Offset 0x020
Reset
Bits
62
63
Figure 20-84
W
W
W
R
R
R
0
g
r
32
0
31
31
Name
SR
g
r
MI
33
30
1
30
CRCU Control Register
CRCU Status Register
g
r
34
Figure 10-44
29
2
29
r
Table 10-42. CRCU Reset Control Register Field Descriptions (continued)
Module initialization resets everything reset by SR, with the exception of the CRCU interrupt mask register.
0 Do not reset
1 Reset most of CRCU
Software reset is functionally equivalent to hardware reset (the RESET# pin), but only for CRCU. All registers
and internal state are returned to their defined reset state. On negation of SW_RESET, the CRCU enters a
routine to perform proper initialization of the S-box.
0 Do not reset
1 Full CRCU reset
n
g
r
35
(respectively g
28
3
28
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
g
r
36
27
4
27
g
r
37
26
5
26
shows the bit position of each coefficient.
g
r
38
6
25
25
g
r
n
39
24
7
24
) represents the n’th residue (respectively polynomial) coefficient. The
Figure 10-44. CRCU Control Register
Figure 10-45. CRCU Status Register
40
8
All zeros
Description
—
—
47 48
IFL
55 56 57
—
23 24 25 26 27 28 29 30 31
55 56 57 58 59 60 61 62 63
g
HALT ICCR
r
7
7
58
g
r
Security Engine (SEC) 3.0
6
6
59 60
g
r
5
Access: Read/Write
5
Access: Read only
g
r
4
4
61
EI
g
r
3
3
0
).
g
r
2
DI
2
62
10-101
g
r
1
1
RD
63
g
r
0
0