MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 173

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDRCLK I DDR controller complex clock (DDRCLK). DDRCLK is the clock source for the DDR memory controller complex
4.2.2
Table 4-3
device, and although some of their functionality is described in
in detail in their respective chapters.
Note that there is also a CLK_OUT signal; the signal driven on the CLK_OUT pin is selectable and
described in
SYSCLK
4.3
This section describes the configuration and control registers that control access to the configuration space
and to the boot code as well as guidelines for accessing these regions. It also contains a brief description
of the boot sequencer which may be used to initialize configuration registers or memory before the CPU
is released to boot.
Freescale Semiconductor
Signal
RTC
I/O
I System clock/PCI clock (SYSCLK/PCI_CLK). SYSCLK is the primary clock input to the MPC8536E. It is the clock
I Real time clock. May be used (optionally) to clock the time base of the e500 core. The RTC timing specifications
Memory Map/Register Definition
describes the overall clock signals. Note that some clock signals are specific to blocks within the
Clock Signals
source for the e500 core and for all devices and interfaces that operate synchronously with the core. It is multiplied
up with a phased-lock loop (PLL) to create the core complex bus (CCB) clock (also called the platform clock), which
is used by virtually all of the synchronous system logic, including the L2 cache, the DDR SDRAM and local bus
memory controllers, and other internal blocks such as the DMA and interrupt controllers. The CCB clock, in turn,
feeds the PLL in the e500 core and the PLL that creates the local bus memory clocks.
When the PCI interface is used, SYSCLK also functions as the PCI_CLK signal. Note that this is true whether the
device is in agent or host mode. The MPC8536E does not provide a separate PCI_CLK output in host mode.
except in the case where synchronous mode of operation is selected (see
Configuration”). This clock input is multipled up with a phased-lock loop (PLL) to create the DDR controller complex
clock. The DDR memory controller complex clock is the DDR data rate on the external interface unless the given
controller is configured to run in half speed (see
are given in the MPC8536E Integrated Processor Hardware Specifications , but the maximum frequency should be
less than one-quarter of the CCB frequency. See
(optionally) to clock the global timers in the programmable interrupt controller (PIC).
Section 23.4.1.25, “Clock Out Control Register (CLKOCR).”
Timing Assertion/Negation—See the MPC8536E Integrated Processor Hardware Specifications for specific
Timing Assertion/Negation—See the MPC8536E Integrated Processor Hardware Specifications for specific
Timing Assertion/Negation—See the MPC8536E Integrated Processor Hardware Specifications for specific
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 4-3. Clock Signals—Detailed Signal Descriptions
timing information for this signal.
timing information for this signal.
timing information for this signal.
Section 23.4.1.24, “DDR Clock Disable Register
Section 4.4.4.4, “Real Time
Description
Section 4.4.4,
Section 4.4.3.3, “DDR PLL Ratio
Clock.” This signal can also be used
“Clocking,” they are defined
Reset, Clocking, and Initialization
(DDRCLKDR)”).
4-3