MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1069

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Bus Interface
The PCI controller provides bus arbitration logic for its master interface and up to five other external PCI
bus masters. The on-chip PCI arbiter is independent of host or agent mode. The on-chip PCI arbiter
functions in both host and agent modes, or it can be disabled to allow for an external PCI arbiter.
A configuration signal sampled at the negation of the reset signal (HRESET) determines if the on-chip PCI
arbiter is enabled (high) or disabled (low). The on-chip PCI arbiter can also be enabled or disabled by
programming bit 15 of the PCI bus arbitration control register (PBACR[PAD]). Note that the sense of
PBACR[PAD] corresponds to the inverse of the configuration signal (that is, when PAD = 0 the arbiter is
enabled, and when PA = 1 the arbiter is disabled). See
Chapter 4, “Reset, Clocking, and Initialization,”
for
more information on the reset configuration signals.
If the on-chip PCI arbiter is enabled, a request-grant pair of signals is provided for each external master
(PCI_REQ[0:4] and PCI_GNT[0:4]). In addition, there is an internal request/grant pair for the internal
master state machine that governs internal accesses to the PCI interface. If the on-chip PCI arbiter is
disabled, the PCI controller uses the PCI_REQ0 signal as an output to issue its request to the external
arbiter and uses the PCI_GNT0 signal as an input to receive its grant from the external arbiter.
The following sections describe the operation of the on-chip PCI arbiter that arbitrates between external
PCI masters and the internal PCI bus master.
16.4.1.1
PCI Bus Arbiter Operation
The on-chip PCI arbiter uses a programmable two-level, round-robin arbitration algorithm. Each of the
five external masters, plus the device itself, can be programmed for two priority levels, high or low, using
the appropriate bits in the PBACR. Within each priority group, the PCI bus grant is asserted to the next
requesting device in numerical order, with the PCI controller positioned before device 0.
Conceptually, the lowest priority device is the master that is currently using the bus, and the highest
priority device is the device that follows the current master in numerical order and group priority. This is
considered to be a fair algorithm, since a single device cannot prevent other devices from having access to
the bus; it automatically becomes the lowest priority device as soon as it begins to use the bus. If a master
is not requesting the bus, then its transaction slot is given to the next requesting device within its priority
group.
A grant is awarded to the highest priority requesting device as soon as the current master begins a
transaction; however, the granted device must wait until the bus is relinquished by the current master
before initiating a transaction.
The grant given to a particular device may be removed and awarded to another higher priority device,
whenever the higher priority device asserts its request. If the bus is idle when a device requests the bus,
then the arbiter withholds the grant for one clock cycle. The arbiter re-evaluates the priorities of all
requesting devices and grants the bus to the highest priority device in the following clock cycle. This
allows a turnaround clock when a higher priority device is using address stepping or when the bus is
parked.
The low-priority group collectively has one bus transaction request slot in the high-priority group. For N
high-priority devices and M low-priority devices, each high-priority device is guaranteed at least 1 of N+1
bus transactions and each low-priority device is guaranteed at least 1 of (N+1) M bus transactions, with
one low-priority device receiving the grant in 1 of N+1 bus transactions. If all devices are programmed to
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Freescale Semiconductor
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