MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1298

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Secure Digital Host Controller
20-24
16–22
DTOE
CEBE
CTOE
Field
CINT
CRM
CCE
CIE
11
12
13
14
15
23
24
Data timeout error. Occurs during one of following timeout conditions:
0 No error
1 Timeout
Command index error. Occurs if a command index error occurs in the command response.
0 No error
1 Timeout
Command end bit error. Occurs when the end bit of a command response is 0.
0 No error
1 End bit error generated
Command CRC error. A command CRC error is generated in two cases:
0 No error
1 CRC error generated
Command timeout error. Occurs if no response is returned within 64 SDHC_CLK cycles from the end bit of the
command. Also, if eSDHC detects a SDHC_CMD line conflict, this bit is set along with IRQSTAT[CCE] as shown in
Table
0 No error
1 Time out
Reserved
Card interrupt.
Writing 1 clears this bit. But, if the interrupt source from the SD card is not cleared, this bit is set again. To clear this
bit, the SD card interrupt source must be cleared followed by writing 1 to this bit.
When this bit is set and the host driver needs to start the interrupt service, IRQSIGEN[CINTIEN] should be cleared
to stop driving the interrupt signal to the host system. After completing the card interrupt service, write 1 to clear this
bit, set IRQSIGEN[CINTIEN], and start sampling the interrupt signal again.
0 No card interrupt
1 Generate card interrupt
Card removal. This bit is set if PRSSTAT[CINS] changes from 1 to 0. When the host driver writes 1 to this bit to clear
it, the status of PRSSTAT[CINS] should be confirmed. Because the card-detect state may be changed when the
host driver clears this bit, an interrupt event may not be generated.
When this bit is cleared, it is set again if no card is inserted. To leave it cleared, clear IRQSTATEN[CRMSEN].
0 Card state unstable or inserted
1 Card removed
• Busy timeout for R1b and R5b types
• Busy timeout after write CRC status
• Read data timeout
• If a response is returned and IRQSTAT[CTOE] is cleared (indicating no timeout), this bit is set when detecting a
• The eSDHC detects a SDHC_CMD line conflict by monitoring the SDHC_CMD line when a command is issued.
• In 1-bit mode, the eSDHC detects the card interrupt without the SD clock to support wakeup.
• In 4-bit mode, the card interrupt signal is sampled during the interrupt cycle. So, there are some sample delays
CRC error in the command response.
If the eSDHC drives the SDHC_CMD line to 1, but detects 0 on the SDHC_CMD line at the next SDHC_CLK
edge, then the eSDHC aborts the command (stop driving SDHC_CMD line) and sets this bit. The CTOE bit is
also set to distinguish the SDHC_CMD line conflict.
between the interrupt signal from the SD card and the interrupt to the host system.
20-27.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 20-14. IRQSTAT Field Descriptions (continued)
Description
Freescale Semiconductor