MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 109

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

About This Book
This reference manual defines the functionality of the MPC8536E. This device integrates a PowerPC™
processor core with system logic required for networking, telecommunications, and wireless infrastructure
applications. The e500v2 processor core is a low-power implementation of the family of reduced
instruction set computing (RISC) embedded processors that implement the Book E definition of the
PowerPC architecture. This book is intended as a companion to the PowerPC e500 Core Complex
Reference Manual.
Audience
It is assumed that the reader understands operating systems, microprocessor system design, and the basic
principles of RISC processing.
Organizations
Following is a summary and a brief description of the major parts of this reference manual:
Part I, “Overview,” describes the many features of the MPC8536E integrated host processor at an overview
level. The following chapters are included:
Freescale Semiconductor
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Chapter 1, “Overview,”
MPC8536E integrated host processor. It describes the MPC8536E, its interfaces, and its
programming model. The functional operation of the MPC8536E with emphasis on peripheral
functions is also described.
Chapter 2, “Memory Map,”
local address map is followed by a description of how local access windows are used to define the
local address map. The inbound and outbound address translation mechanisms used to map to and
from external memory spaces are described next. Finally, the configuration, control, and status
registers are described, including a complete listing of all memory-mapped registers with cross
references to the sections detailing descriptions of each.
Chapter 3, “Signal Descriptions,”
signals that serve multiple functions, output signal states at reset, and reset configuration signals
(and the modes they define).
Chapter 4, “Reset, Clocking, and Initialization,”
reset (POR) sequence, power-on reset configuration, clocking, and initialization of the
MPC8536E.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
provides a high-level description of features and functionality of the
describes the memory map of the MPC8536E. An overview of the
provides a listing of all the external signals, cross-references for
describes the hard and soft resets, the power-on
cix