MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 566

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
To generate an HMAC for a message that is spread across a sequence of descriptors, the following mode
register bit settings should be used:
All descriptors other than the final descriptor must output the intermediate message digest for the next
descriptor to reload as MDEU context.
SSL-MAC operations cannot be spread across a sequence of descriptors.
Additional information on descriptors can be found in
10.7.6.4
Displayed in
HMAC generation. MDEU supports at most one block of key. MDEU generates a key size error if the
value written to this register exceeds 64 bytes for MD5, SHA-1, SHA-224, or SHA-256. If algorithms
SHA-384 or SHA-512 are selected, then MDEU generates a key size error if the value written to this
register exceeds 128 bytes.
10-136
Reset
Field
Addr
R/W
Table 10-62. Mode Register—HMAC Generated Across a Sequence of Descriptors
Table 10-61. Mode Register—HMAC or SSL-MAC Generated by Single Descriptor
Figure
MDEU Key Size Register
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
10-85, this value indicates the number of bytes of key memory that should be used in
Bits
56
59
60
Bits
56
58
59
60
CONT
HMAC
Field
INIT
Figure 10-85. MDEU Key Size Register
—
SMAC
HMAC
CONT
Field
INIT
Descriptor
1 (on)
1 (on)
1 (on)
First
MDEU 0x3_6008
for HMAC
Section 10.3,
R/W
0 (off)
0(on)
1(on)
1(on)
0
Descriptor(s)
Middle
Value
Value
1 (on)
0 (off)
0 (off)
for SSL-MAC
0 (off)
1(on)
1(on)
0(on)
“Descriptors.”
55
Descriptor
56
0 (off)
0 (off)
1 (on)
Final
Key Size
Freescale Semiconductor
63