MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1208

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Express Interface Controller
17-112
Transaction
Outbound
Outbound
Outbound
Outbound
Outbound
response
response
response
response
response
response
Inbound
Inbound
Inbound
Inbound
Inbound
Inbound
Inbound
Inbound
Inbound
request
request
request
request
request
request
request
request
Type
Poisoned TLP (EP=1) response for
Configuration transaction that
originates from
PEX_CONFIG_ADDR/
PEX_CONFIG_DATA
ECRC error response for
Configuration transaction that
originates from
PEX_CONFIG_ADDR/
PEX_CONFIG_DATA
Configuration Request Retry
Status (CRS) response for
Configuration transaction that
originates from ATMU
UR response for Configuration
transaction that originates from
ATMU
CA response for Configuration
transaction that originates from
ATMU
Malformed TLP response
Poisoned TLP (EP=1)
ECRC error
PCI Express nullified request
Outbound ATMU crossing
Illegal message size
Illegal I/O size
Illegal I/O address
Illegal configuration size
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Error Type
Table 17-126. Error Conditions (continued)
1. Send back all 1s (0xFFFF_FFFF) data.
2. Log the error (PCI Express Uncorrectable Status Register[12]) and
send interrupt to PIC, if enabled.
1. Send back all 1s (0xFFFF_FFFF) data.
2. Log the error (PCI Express Uncorrectable Status Register[19]) and
send interrupt to PIC, if enabled.
1.The controller always retries the transaction as soon as possible until
2. Log the error (PEX_ERR_DR[CRST]) and send interrupt to the PIC,
if enabled.
Log the error (PEX_ERR_DR[CDNSC] and PCI Express
Uncorrectable Status Register[20]) and send interrupt to PIC, if
enabled.
Log the error (PEX_ERR_DR[PCAC, CDNSC] and PCI Express
Uncorrectable Status Register[15]) and send interrupt to PIC, if
enabled.
PCI Express controller does not pass the response back to the core.
Therefore, a completion timeout error eventually occurs.
1. If it is a posted transaction, the controller drops it.
2. If it is a non-posted transaction, the controller returns a completion
3. Release the proper credits
1. If it is a posted transaction, the controller drops it.
2. If it is a non-posted transaction, the controller returns a completion
3. Release the proper credits
The packet is dropped.
Log the error (PEX_ERR_DR[OAC]). The transaction is not sent out on
the link.
Log the error (PEX_ERR_DR[MIS]). The transaction is not sent out on
the link.
Log the error (PEX_ERR_DR[IOIS]). The transaction is not sent out on
the link.
Log the error (PEX_ERR_DR[IOIA]). The transaction is not sent out on
the link.
Log the error (PEX_ERR_DR[CIS]). The transaction is not sent out on
the link.
a status other than CRS is returned. However, if a CRS status is
returned after the configuration retry timeout
(PEXCONF_RTY_TOR) timer expires, then the controller aborts the
transaction.
with UR status.
with UR status.
Action
Freescale Semiconductor