MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 884

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
14.5.4.3.1
Figure 14-122
Table 14-131
14-136
10–15
Offset 0x00
Reset
Bits
4–5
0
1
2
3
6
7
8
9
W
R PHY
Reset
PHY Reset PHY reset. This bit is cleared by default. This bit is self-clearing.
Reset AN Reset auto-negotiation. This bit is cleared by default and is self-clearing.
Speed[0] Speed selection. This bit defaults to a cleared state and should always be cleared, which corresponds to
Speed[1] Speed selection. This bit defaults to a set state and should always be set, which corresponds to 1000 Mbps
0
0
Enable
Duplex
Name
Full
AN
—
—
—
—
— Speed[0] AN Enable
0
1
describes the fields of the CR register.
describes the definition for the CR register.
Control Register (CR)
0 Normal operation.
1 The internal state of the TBI is reset. This in turn may change the state of the TBI link partner.
Reserved
1000 Mbps speed.Setting this field controls the speed at which the TBI operates. The table for Speed[1]
provides the appropriate encoding. Its default is bit[2] = ‘0’; bit[9] = ’1’.
Auto-negotiation enable. This bit is set by default.
0 The values programmed in bits 2, 7 and 9 determine the operating condition of the link.
1 Auto-negotiation process enabled.
Reserved
0 Normal operation.
1 The auto-negotiation process restarts. This action is only available if auto-negotiation is enabled.
Duplex mode. This bit is set by default.
0 Reserved.
1 Full-duplex operation.
Reserved, should be cleared.
speed.Setting this field controls the speed at which the TBI operates. The following table provides the
appropriate encoding. Its default is bit[2] = ‘0’; bit[9] = ’1’.
Reserved
0
2
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
3
1
Figure 14-122. Control Register Definition
Table 14-131. CR Field Descriptions
Reserved
Reserved
1000 Mbps
Reserved
0
4
Maximum Operating Speed
—
0
5
Reset AN Full Duplex — Speed[1]
0
6
Description
1
7
8
0
Bit 2
0
1
0
1
1
9
Bit 9
0
0
1
1
10
0
0
Freescale Semiconductor
0
Access: Read/Write
—
0
0
15
0