MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 494

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Offset 0x3_4030
Reset
Security Engine (SEC) 3.0
10.7.1.7
The AESU interrupt status register indicates which unmasked errors have occurred and have generated
error interrupts to the channel. Each bit in this register can only be set if the corresponding bit of the AESU
interrupt mask register is zero (see
interrupt mask register bit is set, the corresponding AESU interrupt status bit is always zero regardless of
the error status.
If the AESU interrupt status register is non-zero, the AESU halts and the AESU error interrupt signal is
asserted to the controller (see
AESU is being operated through channel-controlled access, then an interrupt signal is generated to the
channel to which this EU is assigned. The EU error then appears in bit 55 of the channel status register
(see
Interrupt status register bits can be set by writes from the host, but only if the corresponding bit is cleared
in the interrupt mask register. Bits masked by the interrupt mask register bits are always zero.
The AESU interrupt status and interrupt mask registers can be cleared by programming the AESU reset
control register, as described in
The AESU interrupt status register fields are shown in
Table
10-64
W
R
Table
0
0–48
Bits
10-27.
49
50
51
10-15) and generates a channel error interrupt to the controller.
AESU Interrupt Status Register
Name
ICE
—
—
IE
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 10-27. AESU Interrupt Status Register Field Descriptions
Reserved
Integrity Check Error:
0 No error detected
1 Integrity check error detected. An ICV check was performed and the supplied ICV did
Reserved
Internal Error. An internal processing error was detected while the AESU was processing.
0 No error detected
1 Internal error
Note: This bit is asserted any time an enabled error condition occurs and can only be
not match the one computed by the AESU.
Section 10.5.4.2.2, “Interrupt Status Register
Figure 10-26. AESU Interrupt Status Register
Section 10.7.1.5, “AESU Reset Control
cleared by setting the corresponding bit in the interrupt mask register or by resetting
the AESU.
Section 10.7.1.8, “AESU Interrupt Mask
48
ICE
49
—
50 51
All zeros
IE ERE CE KSE DSE ME AE OFE IFE
Figure
52
Description
53
10-26. These fields are described in
54
55
Register”.
56
(ISR)”). In addition, if the
Register”). If an AESU
57
58
Freescale Semiconductor
59 60
—
Access: Read only
IFO OFU
61
62
—
63
ICE
63